Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3768	1			T22	8		T58	2		T79	16
values[1]	4082	1			T19	8		T57	21		T63	20
values[2]	3401	1			T3	12		T16	4		T59	14
values[3]	3204	1			T60	16		T61	20		T98	20
values[4]	4595	1			T17	2		T110	4		T122	10
values[5]	3738	1			T15	25		T125	6		T77	6
values[6]	4132	1			T101	14		T78	8		T49	73
values[7]	3816	1			T20	6		T118	16		T203	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3680	1			T57	21		T58	2		T60	16
values[1]	4487	1			T15	25		T77	6		T202	4
values[2]	3618	1			T212	14		T367	2		T97	46
values[3]	3856	1			T19	8		T22	8		T78	8
values[4]	3986	1			T16	4		T20	6		T203	4
values[5]	4006	1			T3	12		T17	2		T125	6
values[6]	3572	1			T59	14		T110	4		T101	14
values[7]	3531	1			T122	10		T214	18		T118	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30001

1

T3

12

T15

25

T16

4

auto[1]

735

1

T60

2

T61

2

T66

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	470	1			T58	2		T69	20		T70	20
auto[0]	values[0]	values[1]	592	1			T62	25		T279	18		T249	68
auto[0]	values[0]	values[2]	281	1			T212	14		T367	2		T264	20
auto[0]	values[0]	values[3]	476	1			T22	8		T69	20		T230	16
auto[0]	values[0]	values[4]	395	1			T308	10		T334	12		T53	20
auto[0]	values[0]	values[5]	614	1			T79	16		T251	40		T335	114
auto[0]	values[0]	values[6]	284	1			T74	20		T294	8		T361	40
auto[0]	values[0]	values[7]	576	1			T214	18		T69	34		T73	31
auto[0]	values[1]	values[0]	497	1			T57	21		T65	18		T74	32
auto[0]	values[1]	values[1]	800	1			T73	70		T304	10		T240	90
auto[0]	values[1]	values[2]	352	1			T75	79		T273	19		T236	22
auto[0]	values[1]	values[3]	531	1			T19	8		T229	10		T70	17
auto[0]	values[1]	values[4]	493	1			T63	20		T102	20		T206	50
auto[0]	values[1]	values[5]	505	1			T321	6		T300	10		T270	12
auto[0]	values[1]	values[6]	375	1			T89	10		T368	12		T369	19
auto[0]	values[1]	values[7]	438	1			T74	20		T75	88		T53	21
auto[0]	values[2]	values[0]	180	1			T324	14		T307	20		T312	6
auto[0]	values[2]	values[1]	570	1			T69	23		T70	75		T314	14
auto[0]	values[2]	values[2]	612	1			T316	6		T240	55		T241	29
auto[0]	values[2]	values[3]	261	1			T205	18		T284	10		T206	25
auto[0]	values[2]	values[4]	524	1			T16	4		T65	20		T250	18
auto[0]	values[2]	values[5]	422	1			T3	12		T66	12		T52	65
auto[0]	values[2]	values[6]	424	1			T59	14		T213	16		T285	20
auto[0]	values[2]	values[7]	307	1			T297	4		T75	20		T206	20
auto[0]	values[3]	values[0]	515	1			T60	14		T75	30		T370	8
auto[0]	values[3]	values[1]	337	1			T72	40		T75	20		T247	18
auto[0]	values[3]	values[2]	297	1			T98	20		T322	6		T342	6
auto[0]	values[3]	values[3]	421	1			T249	20		T251	48		T371	14
auto[0]	values[3]	values[4]	363	1			T168	19		T273	19		T236	35
auto[0]	values[3]	values[5]	358	1			T325	2		T366	4		T372	12
auto[0]	values[3]	values[6]	367	1			T61	18		T73	31		T240	95
auto[0]	values[3]	values[7]	450	1			T124	72		T168	32		T286	19
auto[0]	values[4]	values[0]	609	1			T268	129		T249	26		T159	20
auto[0]	values[4]	values[1]	720	1			T246	24		T70	72		T72	102
auto[0]	values[4]	values[2]	680	1			T97	46		T73	81		T164	31
auto[0]	values[4]	values[3]	508	1			T337	10		T102	19		T52	76
auto[0]	values[4]	values[4]	474	1			T207	18		T70	121		T364	6
auto[0]	values[4]	values[5]	338	1			T17	2		T71	16		T344	10
auto[0]	values[4]	values[6]	497	1			T110	4		T65	27		T72	27
auto[0]	values[4]	values[7]	664	1			T122	10		T206	64		T53	20
auto[0]	values[5]	values[0]	531	1			T303	6		T92	27		T241	24
auto[0]	values[5]	values[1]	519	1			T15	25		T77	6		T62	20
auto[0]	values[5]	values[2]	534	1			T70	93		T53	20		T292	24
auto[0]	values[5]	values[3]	477	1			T267	6		T67	4		T69	21
auto[0]	values[5]	values[4]	366	1			T373	10		T206	17		T53	20
auto[0]	values[5]	values[5]	390	1			T125	6		T102	20		T72	40
auto[0]	values[5]	values[6]	492	1			T280	6		T52	68		T262	20
auto[0]	values[5]	values[7]	339	1			T276	12		T249	49		T52	20
auto[0]	values[6]	values[0]	355	1			T290	2		T69	18		T273	20
auto[0]	values[6]	values[1]	554	1			T202	4		T215	6		T326	8
auto[0]	values[6]	values[2]	311	1			T362	6		T242	23		T293	41
auto[0]	values[6]	values[3]	543	1			T78	8		T249	19		T240	65
auto[0]	values[6]	values[4]	470	1			T279	35		T52	20		T243	8
auto[0]	values[6]	values[5]	831	1			T49	73		T73	18		T354	14
auto[0]	values[6]	values[6]	492	1			T101	14		T64	10		T53	20
auto[0]	values[6]	values[7]	480	1			T197	6		T52	20		T320	4
auto[0]	values[7]	values[0]	434	1			T194	2		T365	6		T348	20
auto[0]	values[7]	values[1]	300	1			T121	20		T69	23		T72	74
auto[0]	values[7]	values[2]	476	1			T257	14		T206	19		T273	19
auto[0]	values[7]	values[3]	564	1			T69	20		T343	4		T72	144
auto[0]	values[7]	values[4]	803	1			T20	6		T203	4		T72	358
auto[0]	values[7]	values[5]	438	1			T274	16		T88	22		T65	24
auto[0]	values[7]	values[6]	539	1			T201	20		T98	20		T288	2
auto[0]	values[7]	values[7]	186	1			T118	16		T301	4		T374	6
auto[1]	values[0]	values[0]	11	1			T358	2		T363	2		T375	1
auto[1]	values[0]	values[1]	13	1			T279	2		T249	1		T242	1
auto[1]	values[0]	values[2]	8	1			T355	1		T376	2		T377	2
auto[1]	values[0]	values[3]	1	1			T378	1		-	-		-	-
auto[1]	values[0]	values[4]	11	1			T355	1		T358	1		T332	1
auto[1]	values[0]	values[5]	11	1			T251	1		T241	1		T189	1
auto[1]	values[0]	values[6]	8	1			T361	1		T170	1		T363	3
auto[1]	values[0]	values[7]	17	1			T69	1		T73	1		T206	2
auto[1]	values[1]	values[0]	18	1			T65	2		T74	7		T241	1
auto[1]	values[1]	values[1]	11	1			T240	2		T299	3		T331	1
auto[1]	values[1]	values[2]	5	1			T75	2		T273	1		T379	1
auto[1]	values[1]	values[3]	8	1			T70	3		T72	2		T75	1
auto[1]	values[1]	values[4]	10	1			T206	1		T186	2		T376	2
auto[1]	values[1]	values[5]	20	1			T350	4		T168	1		T259	4
auto[1]	values[1]	values[6]	11	1			T369	1		T380	2		T381	4
auto[1]	values[1]	values[7]	8	1			T75	1		T382	2		T383	2
auto[1]	values[2]	values[0]	12	1			T384	6		T385	3		T386	3
auto[1]	values[2]	values[1]	17	1			T69	1		T70	4		T273	2
auto[1]	values[2]	values[2]	18	1			T240	2		T241	2		T259	4
auto[1]	values[2]	values[3]	4	1			T206	1		T387	1		T388	1
auto[1]	values[2]	values[4]	9	1			T262	1		T238	1		T169	1
auto[1]	values[2]	values[5]	22	1			T66	8		T52	2		T236	1
auto[1]	values[2]	values[6]	15	1			T389	1		T390	1		T189	4
auto[1]	values[2]	values[7]	4	1			T386	2		T391	2		-	-
auto[1]	values[3]	values[0]	11	1			T60	2		T259	2		T245	2
auto[1]	values[3]	values[1]	19	1			T369	2		T355	4		T347	2
auto[1]	values[3]	values[2]	9	1			T340	2		T266	2		T376	2
auto[1]	values[3]	values[3]	9	1			T251	3		T259	2		T387	4
auto[1]	values[3]	values[4]	12	1			T168	1		T273	1		T348	3
auto[1]	values[3]	values[5]	4	1			T273	1		T331	1		T392	1
auto[1]	values[3]	values[6]	12	1			T61	2		T73	1		T383	5
auto[1]	values[3]	values[7]	20	1			T124	3		T168	2		T286	1
auto[1]	values[4]	values[0]	5	1			T268	1		T242	1		T363	1
auto[1]	values[4]	values[1]	14	1			T206	1		T262	1		T360	2
auto[1]	values[4]	values[2]	11	1			T189	1		T384	1		T383	3
auto[1]	values[4]	values[3]	18	1			T102	1		T393	2		T286	4
auto[1]	values[4]	values[4]	13	1			T70	2		T293	2		T238	1
auto[1]	values[4]	values[5]	10	1			T71	4		T275	1		T330	1
auto[1]	values[4]	values[6]	16	1			T72	1		T249	1		T273	2
auto[1]	values[4]	values[7]	18	1			T206	2		T259	1		T253	1
auto[1]	values[5]	values[0]	15	1			T287	3		T293	3		T258	2
auto[1]	values[5]	values[1]	5	1			T287	1		T245	1		T186	1
auto[1]	values[5]	values[2]	10	1			T70	1		T299	2		T394	1
auto[1]	values[5]	values[3]	14	1			T279	4		T347	1		T331	2
auto[1]	values[5]	values[4]	12	1			T206	3		T259	1		T395	2
auto[1]	values[5]	values[5]	16	1			T286	2		T236	1		T287	1
auto[1]	values[5]	values[6]	7	1			T52	1		T236	1		T363	1
auto[1]	values[5]	values[7]	11	1			T245	2		T330	3		T238	3
auto[1]	values[6]	values[0]	12	1			T69	3		T387	4		T377	2
auto[1]	values[6]	values[1]	11	1			T168	1		T355	2		T41	2
auto[1]	values[6]	values[2]	3	1			T242	1		T239	1		T172	1
auto[1]	values[6]	values[3]	15	1			T249	1		T286	1		T253	2
auto[1]	values[6]	values[4]	12	1			T279	3		T273	2		T281	1
auto[1]	values[6]	values[5]	18	1			T73	2		T259	1		T237	1
auto[1]	values[6]	values[6]	15	1			T53	1		T186	2		T369	5
auto[1]	values[6]	values[7]	10	1			T236	2		T396	1		T245	2
auto[1]	values[7]	values[0]	5	1			T332	2		T172	3		-	-
auto[1]	values[7]	values[1]	5	1			T279	3		T357	1		T170	1
auto[1]	values[7]	values[2]	11	1			T206	1		T273	1		T186	1
auto[1]	values[7]	values[3]	6	1			T248	1		T397	4		T390	1
auto[1]	values[7]	values[4]	19	1			T72	2		T73	1		T74	4
auto[1]	values[7]	values[5]	9	1			T65	2		T299	1		T237	2
auto[1]	values[7]	values[6]	18	1			T251	2		T241	7		T299	2
auto[1]	values[7]	values[7]	3	1			T170	2		T398	1		-	-