Group : spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_addr_4b_en 2 0 2 100.00 100 1 1 2
cp_prev_addr_4b_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1619 1 T19 2 T23 4 T57 2
auto[1] 1582 1 T15 2 T23 6 T49 2



Summary for Variable cp_prev_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1631 1 T19 1 T23 3 T57 1
auto[1] 1570 1 T15 2 T19 1 T23 7



Summary for Cross cr_all

Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_addr_4b_encp_prev_addr_4b_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 863 1 T19 1 T23 1 T57 1
auto[0] auto[1] 756 1 T19 1 T23 3 T57 1
auto[1] auto[0] 768 1 T23 2 T49 1 T55 1
auto[1] auto[1] 814 1 T15 2 T23 4 T49 1

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