Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	857	1			T24	11		T34	27		T35	14
all_values[1]	857	1			T24	11		T34	27		T35	14
all_values[2]	857	1			T24	11		T34	27		T35	14
all_values[3]	857	1			T24	11		T34	27		T35	14
all_values[4]	857	1			T24	11		T34	27		T35	14
all_values[5]	857	1			T24	11		T34	27		T35	14
all_values[6]	857	1			T24	11		T34	27		T35	14
all_values[7]	857	1			T24	11		T34	27		T35	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3598

1

T24

47

T34

114

T35

62

auto[1]

3258

1

T24

41

T34

102

T35

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2690

1

T24

37

T34

74

T35

30

auto[1]

4166

1

T24

51

T34

142

T35

82

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3897

1

T24

51

T34

106

T35

56

auto[1]

2959

1

T24

37

T34

110

T35

56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T24	1		T34	1		T36	2
all_values[0]	auto[0]	auto[0]	auto[1]	99	1			T24	1		T34	4		T35	1
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T24	2		T34	6		T35	2
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T24	2		T34	1		T35	3
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T24	4		T34	7		T36	5
all_values[0]	auto[1]	auto[1]	auto[1]	190	1			T24	1		T34	8		T35	8
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T24	1		T34	2		T35	4
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T24	1		T34	4		T35	2
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T24	5		T34	5		T36	2
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T35	2		T36	3		T37	2
all_values[1]	auto[1]	auto[0]	auto[1]	188	1			T24	1		T34	10		T35	3
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T24	3		T34	6		T35	3
all_values[2]	auto[0]	auto[0]	auto[0]	153	1			T34	5		T35	5		T36	2
all_values[2]	auto[0]	auto[0]	auto[1]	91	1			T24	4		T34	4		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T34	2		T36	5		T37	6
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T24	1		T34	2		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T24	4		T34	8		T35	4
all_values[2]	auto[1]	auto[1]	auto[1]	182	1			T24	2		T34	6		T35	3
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T24	3		T34	5		T35	2
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T34	3		T35	4		T37	4
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T24	2		T34	7		T35	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T24	2		T34	2		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	205	1			T24	2		T34	4		T35	4
all_values[3]	auto[1]	auto[1]	auto[1]	159	1			T24	2		T34	6		T35	2
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T24	2		T34	2		T35	3
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T24	1		T34	2		T35	1
all_values[4]	auto[0]	auto[1]	auto[0]	147	1			T24	2		T34	3		T35	1
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T34	3		T35	2		T36	2
all_values[4]	auto[1]	auto[0]	auto[1]	214	1			T24	4		T34	11		T35	4
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T24	2		T34	6		T35	3
all_values[5]	auto[0]	auto[0]	auto[0]	270	1			T24	6		T34	10		T35	6
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T24	2		T34	3		T35	3
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T24	1		T34	4		T35	2
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T24	2		T34	10		T35	3
all_values[6]	auto[0]	auto[0]	auto[0]	188	1			T24	6		T34	6		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T34	2		T35	2		T37	5
all_values[6]	auto[0]	auto[1]	auto[0]	170	1			T24	2		T34	3		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	94	1			T34	2		T36	1		T37	2
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T24	1		T34	8		T35	6
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T24	2		T34	6		T35	4
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T24	2		T34	6		T37	7
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T35	2		T36	3		T99	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T24	1		T34	8		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	94	1			T24	2		T34	3		T35	4
all_values[7]	auto[1]	auto[0]	auto[1]	193	1			T24	2		T34	6		T35	5
all_values[7]	auto[1]	auto[1]	auto[1]	183	1			T24	4		T34	4		T35	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal