Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T5

7

T6

1

T7

3

auto[1]

1879

1

T5

7

T6

4

T7

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2070

1

T6

5

T9

7

T46

6

auto[1]

1679

1

T5

14

T7

8

T14

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2953

1

T5

14

T6

3

T7

8

auto[1]

796

1

T6

2

T9

5

T46

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	715	1			T5	2		T7	1		T9	1
valid[1]	784	1			T5	4		T6	1		T7	3
valid[2]	743	1			T5	4		T6	2		T7	1
valid[3]	723	1			T5	1		T6	1		T9	3
valid[4]	784	1			T5	3		T6	1		T7	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T47	1		T48	1		T201	2
auto[0]	auto[0]	valid[0]	auto[1]	152	1			T5	1		T7	1		T30	2
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T46	1		T48	1		T100	1
auto[0]	auto[0]	valid[1]	auto[1]	182	1			T5	1		T7	1		T14	2
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T201	2		T56	2		T108	2
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T5	3		T14	1		T26	1
auto[0]	auto[0]	valid[3]	auto[0]	130	1			T48	2		T100	3		T201	1
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T14	2		T30	4		T76	2
auto[0]	auto[0]	valid[4]	auto[0]	138	1			T48	1		T108	3		T35	1
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T5	2		T7	1		T14	3
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T48	1		T100	1		T201	1
auto[0]	auto[1]	valid[0]	auto[1]	148	1			T5	1		T14	1		T26	2
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T6	1		T9	1		T47	2
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T5	3		T7	2		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T6	2		T100	3		T201	1
auto[0]	auto[1]	valid[2]	auto[1]	157	1			T5	1		T7	1		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	123	1			T9	1		T47	2		T48	1
auto[0]	auto[1]	valid[3]	auto[1]	179	1			T5	1		T14	1		T26	3
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T47	1		T48	2		T100	1
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T5	1		T7	2		T14	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T9	1		T47	1		T48	2
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T48	1		T62	1		T91	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T46	1		T201	1		T56	1
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T6	1		T9	1		T100	1
auto[1]	auto[0]	valid[4]	auto[0]	90	1			T46	1		T108	1		T411	1
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T46	1		T35	1		T99	1
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T9	2		T47	1		T48	1
auto[1]	auto[1]	valid[2]	auto[0]	92	1			T47	1		T48	3		T116	1
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T9	1		T46	1		T48	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T6	1		T46	1		T47	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal