Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52442

1

T6

194

T9

268

T29

8

auto[1]

17643

1

T5

14

T7

84

T14

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51070

1

T5

14

T6

126

T7

84

auto[1]

19015

1

T6

68

T9

85

T29

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36061	1			T5	14		T6	95		T7	44
others[1]	5931	1			T6	17		T7	7		T9	20
others[2]	5958	1			T6	14		T7	7		T9	20
others[3]	6674	1			T6	15		T7	10		T9	23
interest[1]	3923	1			T6	17		T7	2		T9	14
interest[4]	23480	1			T5	14		T6	57		T7	27
interest[64]	11538	1			T6	36		T7	14		T9	56

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17103	1			T6	62		T9	98		T29	1
auto[0]	auto[0]	others[1]	2848	1			T6	9		T9	13		T45	2
auto[0]	auto[0]	others[2]	2861	1			T6	11		T9	13		T46	12
auto[0]	auto[0]	others[3]	3156	1			T6	9		T9	12		T29	1
auto[0]	auto[0]	interest[1]	1864	1			T6	9		T9	10		T46	8
auto[0]	auto[0]	interest[4]	11083	1			T6	36		T9	68		T29	1
auto[0]	auto[0]	interest[64]	5595	1			T6	26		T9	37		T29	1
auto[0]	auto[1]	others[0]	9250	1			T5	14		T7	44		T14	12
auto[0]	auto[1]	others[1]	1485	1			T7	7		T26	19		T30	45
auto[0]	auto[1]	others[2]	1479	1			T7	7		T26	24		T30	38
auto[0]	auto[1]	others[3]	1636	1			T7	10		T26	21		T30	55
auto[0]	auto[1]	interest[1]	991	1			T7	2		T26	12		T30	23
auto[0]	auto[1]	interest[4]	6178	1			T5	14		T7	27		T14	12
auto[0]	auto[1]	interest[64]	2802	1			T7	14		T26	31		T30	70
auto[1]	auto[0]	others[0]	9708	1			T6	33		T9	37		T29	1
auto[1]	auto[0]	others[1]	1598	1			T6	8		T9	7		T29	1
auto[1]	auto[0]	others[2]	1618	1			T6	3		T9	7		T29	1
auto[1]	auto[0]	others[3]	1882	1			T6	6		T9	11		T45	2
auto[1]	auto[0]	interest[1]	1068	1			T6	8		T9	4		T29	2
auto[1]	auto[0]	interest[4]	6219	1			T6	21		T9	22		T29	1
auto[1]	auto[0]	interest[64]	3141	1			T6	10		T9	19		T46	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal