Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2669325	1			T1	1		T2	1		T3	1
all_values[1]	2669325	1			T1	1		T2	1		T3	1
all_values[2]	2669325	1			T1	1		T2	1		T3	1
all_values[3]	2669325	1			T1	1		T2	1		T3	1
all_values[4]	2669325	1			T1	1		T2	1		T3	1
all_values[5]	2669325	1			T1	1		T2	1		T3	1
all_values[6]	2669325	1			T1	1		T2	1		T3	1
all_values[7]	2669325	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20560012

1

T1

8

T2

8

T3

8

auto[1]

794588

1

T34

48655

T35

5725

T37

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21328371

1

T1

8

T2

8

T3

8

auto[1]

26229

1

T147

2

T80

1

T99

174

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2524499	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11998	1			T80	1		T99	96		T51	143
all_values[0]	auto[1]	auto[0]	131939	1			T35	1841		T37	2		T175	7
all_values[0]	auto[1]	auto[1]	889	1			T34	2		T35	59		T37	4
all_values[1]	auto[0]	auto[0]	2604986	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7643	1			T99	78		T51	46		T67	106
all_values[1]	auto[1]	auto[0]	56165	1			T34	2		T35	1858		T37	4
all_values[1]	auto[1]	auto[1]	531	1			T34	1		T35	42		T37	3
all_values[2]	auto[0]	auto[0]	2604429	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3154	1			T51	43		T67	18		T34	2
all_values[2]	auto[1]	auto[0]	61511	1			T34	9722		T35	1		T37	4
all_values[2]	auto[1]	auto[1]	231	1			T34	7		T35	3		T37	3
all_values[3]	auto[0]	auto[0]	2525368	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	187	1			T147	2		T34	2		T35	3
all_values[3]	auto[1]	auto[0]	143602	1			T34	9728		T35	4		T37	3
all_values[3]	auto[1]	auto[1]	168	1			T34	2		T35	1		T37	3
all_values[4]	auto[0]	auto[0]	2545786	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	190	1			T34	2		T35	3		T37	3
all_values[4]	auto[1]	auto[0]	123181	1			T34	9728		T35	2		T37	3
all_values[4]	auto[1]	auto[1]	168	1			T34	1		T35	2		T37	3
all_values[5]	auto[0]	auto[0]	2535457	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	149	1			T35	1		T37	2		T175	8
all_values[5]	auto[1]	auto[0]	133551	1			T34	9729		T35	5		T175	7
all_values[5]	auto[1]	auto[1]	168	1			T34	1		T35	1		T37	2
all_values[6]	auto[0]	auto[0]	2543898	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	196	1			T34	2		T37	5		T175	6
all_values[6]	auto[1]	auto[0]	125045	1			T35	3		T37	3		T175	1262
all_values[6]	auto[1]	auto[1]	186	1			T34	2		T35	2		T175	7
all_values[7]	auto[0]	auto[0]	2651885	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	187	1			T34	2		T35	1		T37	3
all_values[7]	auto[1]	auto[0]	17069	1			T34	9728		T35	1897		T37	5
all_values[7]	auto[1]	auto[1]	184	1			T34	2		T35	4		T37	3