Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35766	1			T6	8		T9	4		T10	2
auto[SpiFlashAddrCfg]	8078	1			T10	4		T18	8		T39	4
auto[SpiFlashAddr3b]	10062	1			T6	8		T10	2		T18	8
auto[SpiFlashAddr4b]	8078	1			T6	6		T7	2		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35684

1

T6

22

T7

2

T8

2

auto[1]

26300

1

T10

16

T17

4

T53

19

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32686

1

T6

16

T9

2

T10

6

auto[1]

29298

1

T6

6

T7

2

T8

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40762	1			T6	16		T9	6		T10	4
values[1]	1248	1			T48	4		T55	2		T43	5
values[2]	1568	1			T10	2		T14	2		T39	2
values[3]	1594	1			T10	2		T39	4		T49	1
values[4]	1607	1			T53	5		T136	2		T43	1
values[5]	1616	1			T18	4		T53	1		T43	8
values[6]	1543	1			T14	2		T53	3		T43	6
values[7]	1678	1			T7	2		T8	2		T53	2
values[8]	10368	1			T6	6		T10	8		T18	14

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32350

1

T6

22

T7

2

T8

2

auto[1]

29634

1

T14

4

T49

1

T53

60

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58531

1

T6

20

T7

2

T8

2

write

3453

1

T6

2

T53

2

T59

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20591

1

T6

6

T7

2

T8

2

valids[0x1]

41393

1

T6

16

T9

6

T10

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1672	1			T6	6		T10	2		T39	2
internal_process_ops[0x5a]	1733	1			T10	2		T53	5		T56	2
internal_process_ops[0x05]	21007	1			T6	2		T53	3		T136	2
internal_process_ops[0x35]	1706	1			T17	2		T53	3		T136	2
internal_process_ops[0x15]	1639	1			T9	4		T18	4		T63	2
internal_process_ops[0x03]	1123	1			T6	2		T10	2		T14	2
internal_process_ops[0x0b]	1135	1			T9	2		T17	2		T55	2
internal_process_ops[0x3b]	1170	1			T10	4		T18	2		T43	4
internal_process_ops[0x6b]	1142	1			T10	2		T48	4		T43	4
internal_process_ops[0xbb]	1132	1			T8	2		T14	2		T39	4
internal_process_ops[0xeb]	1118	1			T7	2		T39	2		T136	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60287

1

T6

22

T7

2

T8

2

auto[1]

1697

1

T53

2

T43

7

T45

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59524

1

T6

22

T7

2

T8

2

auto[1]

2460

1

T43

13

T45

5

T54

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11059

1

T6

8

T9

4

T13

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6109

1

T10

2

T17

2

T63

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2252

1

T18

8

T39

4

T55

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1929

1

T10

4

T63

4

T45

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2805

1

T6

8

T18

8

T39

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2383

1

T10

2

T45

15

T64

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2198

1

T6

4

T7

2

T8

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1944

1

T10

8

T17

2

T45

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

135

1

T59

2

T45

2

T205

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T45

1

T66

1

T68

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T66

1

T67

2

T69

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

85

1

T51

1

T68

1

T70

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T58

2

T45

3

T51

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T69

3

T72

1

T206

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

113

1

T45

1

T66

3

T68

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T45

2

T51

2

T67

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T55

2

T56

2

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

131

1

T66

3

T67

1

T68

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T68

1

T34

1

T70

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

125

1

T45

1

T64

2

T66

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

113

1

T6

2

T65

2

T70

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

74

1

T45

3

T51

2

T40

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

81

1

T51

1

T66

3

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T64

6

T68

1

T69

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10394

1

T53

13

T43

38

T54

238

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7370

1

T53

9

T43

22

T54

93

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1591

1

T49

1

T53

13

T48

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1507

1

T53

6

T43

6

T54

31

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2036

1

T53

11

T43

11

T54

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1901

1

T53

4

T43

19

T54

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1558

1

T14

4

T53

2

T48

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1495

1

T43

9

T54

24

T80

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T97

2

T178

1

T207

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T53

1

T80

1

T97

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T43

2

T54

1

T96

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T96

2

T98

1

T99

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

109

1

T43

3

T96

1

T98

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T53

1

T54

1

T208

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T43

1

T54

2

T80

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T97

1

T98

2

T99

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

101

1

T54

3

T97

3

T98

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

138

1

T43

3

T54

1

T98

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

120

1

T97

1

T99

7

T91

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T97

1

T98

2

T99

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

126

1

T43

1

T54

3

T96

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

146

1

T43

3

T96

2

T97

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

132

1

T54

3

T98

2

T99

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T43

1

T54

1

T99

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4142	1			T6	6		T13	10		T57	16
auto[0]	values[0]	valids[0x1]	16031	1			T6	10		T9	6		T10	4
auto[0]	values[1]	valids[0x1]	662	1			T55	2		T209	2		T210	2
auto[0]	values[2]	valids[0x0]	579	1			T10	2		T39	2		T45	1
auto[0]	values[2]	valids[0x1]	325	1			T45	1		T51	3		T67	3
auto[0]	values[3]	valids[0x0]	578	1			T10	2		T39	4		T45	4
auto[0]	values[3]	valids[0x1]	344	1			T63	4		T55	2		T45	6
auto[0]	values[4]	valids[0x0]	599	1			T136	2		T60	2		T45	11
auto[0]	values[4]	valids[0x1]	305	1			T45	2		T66	3		T67	1
auto[0]	values[5]	valids[0x0]	608	1			T45	1		T209	2		T50	4
auto[0]	values[5]	valids[0x1]	286	1			T18	4		T75	4		T51	2
auto[0]	values[6]	valids[0x0]	552	1			T45	3		T51	2		T211	2
auto[0]	values[6]	valids[0x1]	320	1			T45	2		T50	2		T51	2
auto[0]	values[7]	valids[0x0]	655	1			T7	2		T8	2		T45	1
auto[0]	values[7]	valids[0x1]	336	1			T56	2		T51	2		T66	8
auto[0]	values[8]	valids[0x0]	3747	1			T10	4		T18	12		T59	2
auto[0]	values[8]	valids[0x1]	2281	1			T6	6		T10	4		T18	2
auto[1]	values[0]	valids[0x0]	4073	1			T53	12		T43	32		T54	52
auto[1]	values[0]	valids[0x1]	16516	1			T53	15		T43	43		T54	308
auto[1]	values[1]	valids[0x1]	586	1			T48	4		T43	5		T54	6
auto[1]	values[2]	valids[0x0]	399	1			T14	2		T53	4		T43	1
auto[1]	values[2]	valids[0x1]	265	1			T53	1		T54	6		T96	1
auto[1]	values[3]	valids[0x0]	398	1			T43	5		T54	5		T147	1
auto[1]	values[3]	valids[0x1]	274	1			T49	1		T53	2		T43	2
auto[1]	values[4]	valids[0x0]	418	1			T53	3		T43	1		T54	8
auto[1]	values[4]	valids[0x1]	285	1			T53	2		T54	8		T97	1
auto[1]	values[5]	valids[0x0]	432	1			T53	1		T43	4		T54	4
auto[1]	values[5]	valids[0x1]	290	1			T43	4		T54	2		T96	2
auto[1]	values[6]	valids[0x0]	407	1			T53	3		T43	3		T54	5
auto[1]	values[6]	valids[0x1]	264	1			T14	2		T43	3		T54	4
auto[1]	values[7]	valids[0x0]	411	1			T43	2		T54	2		T147	1
auto[1]	values[7]	valids[0x1]	276	1			T53	2		T43	3		T54	3
auto[1]	values[8]	valids[0x0]	2593	1			T53	8		T48	4		T43	20
auto[1]	values[8]	valids[0x1]	1747	1			T53	7		T43	12		T54	25