Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3390933

1

T6

1

T7

165

T8

1

auto[1]

28603

1

T43

916

T45

115

T54

244

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

809622

1

T6

1

T7

165

T8

1

auto[1]

2609914

1

T9

1088

T53

645

T55

266

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	618090	1			T6	1		T7	7		T8	1
auto[524288:1048575]	400970	1			T9	1		T13	10		T39	20
auto[1048576:1572863]	405413	1			T9	75		T14	951		T38	153
auto[1572864:2097151]	393992	1			T9	1056		T13	621		T14	1903
auto[2097152:2621439]	372042	1			T7	158		T9	27		T13	3
auto[2621440:3145727]	404886	1			T9	264		T14	2		T39	305
auto[3145728:3670015]	418238	1			T9	1495		T13	1897		T14	202
auto[3670016:4194303]	405905	1			T13	16		T14	1		T39	559

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645272

1

T6

1

T7

6

T8

1

auto[1]

774264

1

T7

159

T9

4872

T13

3468

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2922104

1

T6

1

T7

165

T8

1

auto[1]

497432

1

T13

2860

T53

385

T57

61

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	176763	1			T6	1		T7	7		T8	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	381309	1			T9	1082		T55	266		T60	2676
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	80244	1			T9	1		T13	6		T39	20
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	256555	1			T45	2308		T54	1192		T96	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	87845	1			T9	74		T14	951		T38	153
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	245063	1			T9	1		T43	2012		T45	263
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	83896	1			T9	1052		T14	1903		T39	300
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	249305	1			T9	4		T45	1		T54	3186
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	90618	1			T7	158		T9	26		T38	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	210186	1			T9	1		T53	4		T45	353
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	93291	1			T9	264		T14	2		T39	305
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	242692	1			T53	256		T43	256		T45	238
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	96919	1			T9	1495		T13	629		T14	202
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	271177	1			T54	2078		T96	256		T97	2000
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	82013	1			T14	1		T39	559		T49	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	250753	1			T53	1		T43	384		T54	703
auto[0]	auto[1]	auto[0:524287]	auto[0]	3747	1			T13	948		T54	2		T120	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	52444	1			T54	257		T51	256		T61	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	673	1			T13	4		T54	1		T299	69
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59736	1			T54	512		T222	256		T251	226
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	600	1			T57	1		T43	6		T51	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68686	1			T43	256		T45	256		T207	257
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2448	1			T13	621		T53	1		T54	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	55519	1			T53	256		T54	641		T97	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1050	1			T13	3		T57	3		T43	54
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	66473	1			T43	901		T34	3036		T91	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	821	1			T57	57		T43	19		T54	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	64297	1			T43	124		T54	1		T98	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	3742	1			T13	1268		T43	2		T54	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43002	1			T54	256		T97	2		T67	2934
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	817	1			T13	16		T43	2		T96	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	68249	1			T53	128		T51	5		T250	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	521	1			T54	3		T96	12		T97	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2665	1			T54	93		T97	54		T98	32
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	440	1			T43	9		T45	2		T99	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2351	1			T45	42		T51	24		T124	128
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	434	1			T43	26		T45	2		T97	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2399	1			T43	321		T45	27		T97	19
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	373	1			T45	1		T54	1		T98	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2049	1			T45	41		T54	1		T98	78
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	408	1			T54	2		T96	6		T97	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2713	1			T54	31		T97	60		T98	38
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	373	1			T54	1		T80	2		T96	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2205	1			T54	29		T124	4		T68	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	408	1			T54	2		T97	1		T99	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2472	1			T54	27		T97	11		T99	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	458	1			T43	14		T96	5		T98	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3206	1			T98	33		T67	4		T250	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	130	1			T54	1		T61	1		T69	31
auto[1]	auto[1]	auto[0:524287]	auto[1]	511	1			T54	3		T61	54		T37	23
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	56	1			T222	8		T245	1		T236	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	915	1			T222	553		T245	1		T236	56
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	61	1			T43	5		T223	1		T251	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	325	1			T223	24		T251	13		T111	47
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T54	1		T69	9		T222	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	314	1			T54	37		T248	1		T111	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	106	1			T43	9		T91	1		T222	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	488	1			T43	91		T91	1		T239	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	108	1			T43	10		T54	1		T69	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1099	1			T43	431		T54	11		T222	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	75	1			T97	1		T250	1		T37	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	443	1			T97	51		T111	6		T189	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	96	1			T251	1		T248	2		T300	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	313	1			T251	26		T300	22		T111	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2133972	1			T6	1		T7	6		T8	1
auto[0]	auto[0]	auto[1]	764657	1			T7	159		T9	4872		T13	631
auto[0]	auto[1]	auto[0]	483446	1			T13	23		T53	385		T57	5
auto[0]	auto[1]	auto[1]	8858	1			T13	2837		T57	56		T54	1
auto[1]	auto[0]	auto[0]	22852	1			T43	366		T45	114		T54	190
auto[1]	auto[0]	auto[1]	623	1			T43	4		T45	1		T96	5
auto[1]	auto[1]	auto[0]	5002	1			T43	542		T54	53		T97	52
auto[1]	auto[1]	auto[1]	126	1			T43	4		T54	1		T91	1