Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2669325	1			T1	1		T2	1		T3	1
all_pins[1]	2669325	1			T1	1		T2	1		T3	1
all_pins[2]	2669325	1			T1	1		T2	1		T3	1
all_pins[3]	2669325	1			T1	1		T2	1		T3	1
all_pins[4]	2669325	1			T1	1		T2	1		T3	1
all_pins[5]	2669325	1			T1	1		T2	1		T3	1
all_pins[6]	2669325	1			T1	1		T2	1		T3	1
all_pins[7]	2669325	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21225361	1			T1	8		T2	8		T3	8
values[0x1]	129239	1			T34	267		T35	123		T37	21
transitions[0x0=>0x1]	126668	1			T34	263		T35	77		T37	15
transitions[0x1=>0x0]	126683	1			T34	264		T35	77		T37	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2668372	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	953	1			T34	2		T35	64		T37	4
all_pins[0]	transitions[0x0=>0x1]	693	1			T34	2		T35	20		T37	4
all_pins[0]	transitions[0x1=>0x0]	305	1			T34	1		T35	2		T37	3
all_pins[1]	values[0x0]	2668760	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	565	1			T34	1		T35	46		T37	3
all_pins[1]	transitions[0x0=>0x1]	496	1			T35	45		T37	1		T175	3
all_pins[1]	transitions[0x1=>0x0]	168	1			T34	7		T35	2		T37	1
all_pins[2]	values[0x0]	2669088	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	237	1			T34	8		T35	3		T37	3
all_pins[2]	transitions[0x0=>0x1]	192	1			T34	8		T35	3		T37	1
all_pins[2]	transitions[0x1=>0x0]	123	1			T34	2		T35	1		T37	1
all_pins[3]	values[0x0]	2669157	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	168	1			T34	2		T35	1		T37	3
all_pins[3]	transitions[0x0=>0x1]	119	1			T34	2		T35	1		T37	1
all_pins[3]	transitions[0x1=>0x0]	119	1			T34	1		T35	2		T37	1
all_pins[4]	values[0x0]	2669157	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	168	1			T34	1		T35	2		T37	3
all_pins[4]	transitions[0x0=>0x1]	129	1			T34	1		T35	2		T37	3
all_pins[4]	transitions[0x1=>0x0]	2368	1			T34	249		T35	1		T37	2
all_pins[5]	values[0x0]	2666918	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	2407	1			T34	249		T35	1		T37	2
all_pins[5]	transitions[0x0=>0x1]	393	1			T34	249		T35	1		T37	2
all_pins[5]	transitions[0x1=>0x0]	122543	1			T34	2		T35	2		T175	1252
all_pins[6]	values[0x0]	2544768	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	124557	1			T34	2		T35	2		T175	1253
all_pins[6]	transitions[0x0=>0x1]	124507	1			T34	1		T35	2		T175	1247
all_pins[6]	transitions[0x1=>0x0]	134	1			T34	1		T35	4		T37	3
all_pins[7]	values[0x0]	2669141	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	184	1			T34	2		T35	4		T37	3
all_pins[7]	transitions[0x0=>0x1]	139	1			T35	3		T37	3		T175	8
all_pins[7]	transitions[0x1=>0x0]	923	1			T34	1		T35	63		T37	4