Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19183

1

T6

22

T7

2

T8

2

auto[1]

13167

1

T10

16

T17

4

T63

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4044	1			T17	4		T45	116		T210	6
values[1]	4134	1			T136	6		T45	40		T284	12
values[2]	4191	1			T13	10		T18	22		T56	8
values[3]	4468	1			T8	2		T9	6		T59	6
values[4]	3927	1			T10	16		T45	20		T255	18
values[5]	3700	1			T7	2		T39	8		T63	6
values[6]	3299	1			T6	22		T58	2		T45	29
values[7]	4587	1			T51	20		T211	4		T273	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3917	1			T9	6		T56	8		T45	145
values[1]	4244	1			T63	6		T228	12		T284	12
values[2]	4697	1			T13	10		T39	8		T75	4
values[3]	3726	1			T57	16		T55	12		T51	40
values[4]	4138	1			T136	6		T59	6		T269	2
values[5]	3509	1			T6	22		T10	16		T17	4
values[6]	4574	1			T8	2		T60	14		T255	18
values[7]	3545	1			T7	2		T18	22		T58	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	401	1			T45	101		T34	14		T244	13
auto[0]	values[0]	values[1]	314	1			T272	16		T69	20		T206	13
auto[0]	values[0]	values[2]	433	1			T51	15		T68	13		T266	20
auto[0]	values[0]	values[3]	173	1			T51	8		T298	14		T233	15
auto[0]	values[0]	values[4]	463	1			T189	12		T301	14		T259	166
auto[0]	values[0]	values[5]	236	1			T210	6		T302	8		T247	18
auto[0]	values[0]	values[6]	377	1			T66	16		T257	20		T41	60
auto[0]	values[0]	values[7]	204	1			T205	46		T71	11		T248	11
auto[0]	values[1]	values[0]	278	1			T65	45		T69	14		T237	14
auto[0]	values[1]	values[1]	370	1			T284	12		T303	4		T189	31
auto[0]	values[1]	values[2]	447	1			T286	10		T271	21		T233	8
auto[0]	values[1]	values[3]	276	1			T304	18		T236	8		T189	16
auto[0]	values[1]	values[4]	311	1			T136	6		T269	2		T68	42
auto[0]	values[1]	values[5]	197	1			T45	10		T93	20		T40	14
auto[0]	values[1]	values[6]	388	1			T51	38		T305	14		T306	26
auto[0]	values[1]	values[7]	189	1			T61	12		T307	14		T234	6
auto[0]	values[2]	values[0]	348	1			T56	8		T72	54		T189	11
auto[0]	values[2]	values[1]	416	1			T68	16		T275	12		T239	10
auto[0]	values[2]	values[2]	357	1			T13	10		T209	4		T268	24
auto[0]	values[2]	values[3]	401	1			T206	14		T244	12		T252	97
auto[0]	values[2]	values[4]	213	1			T308	13		T42	10		T309	22
auto[0]	values[2]	values[5]	225	1			T66	8		T69	11		T70	11
auto[0]	values[2]	values[6]	383	1			T67	7		T310	8		T206	23
auto[0]	values[2]	values[7]	252	1			T18	22		T311	2		T92	6
auto[0]	values[3]	values[0]	331	1			T9	6		T51	12		T69	8
auto[0]	values[3]	values[1]	495	1			T51	10		T69	7		T40	9
auto[0]	values[3]	values[2]	330	1			T75	4		T67	8		T206	11
auto[0]	values[3]	values[3]	239	1			T236	10		T189	9		T270	16
auto[0]	values[3]	values[4]	405	1			T59	6		T51	12		T69	11
auto[0]	values[3]	values[5]	214	1			T52	12		T69	7		T175	7
auto[0]	values[3]	values[6]	330	1			T8	2		T60	14		T51	15
auto[0]	values[3]	values[7]	219	1			T51	16		T69	24		T312	10
auto[0]	values[4]	values[0]	245	1			T72	16		T189	29		T232	11
auto[0]	values[4]	values[1]	303	1			T206	11		T175	11		T166	8
auto[0]	values[4]	values[2]	441	1			T313	2		T70	13		T252	75
auto[0]	values[4]	values[3]	276	1			T51	11		T100	4		T189	10
auto[0]	values[4]	values[4]	275	1			T66	13		T69	11		T239	15
auto[0]	values[4]	values[5]	284	1			T72	8		T314	12		T232	14
auto[0]	values[4]	values[6]	250	1			T255	18		T72	13		T236	15
auto[0]	values[4]	values[7]	231	1			T45	9		T315	12		T189	12
auto[0]	values[5]	values[0]	250	1			T299	14		T66	15		T34	7
auto[0]	values[5]	values[1]	265	1			T285	2		T243	18		T193	69
auto[0]	values[5]	values[2]	187	1			T39	8		T247	12		T264	12
auto[0]	values[5]	values[3]	335	1			T57	16		T55	12		T267	12
auto[0]	values[5]	values[4]	329	1			T70	15		T248	11		T40	12
auto[0]	values[5]	values[5]	221	1			T45	15		T62	22		T40	36
auto[0]	values[5]	values[6]	336	1			T316	20		T248	16		T317	10
auto[0]	values[5]	values[7]	222	1			T7	2		T51	4		T206	9
auto[0]	values[6]	values[0]	280	1			T45	15		T50	12		T67	16
auto[0]	values[6]	values[1]	217	1			T228	12		T72	9		T232	10
auto[0]	values[6]	values[2]	350	1			T67	7		T69	15		T318	4
auto[0]	values[6]	values[3]	246	1			T236	12		T319	12		T320	12
auto[0]	values[6]	values[4]	201	1			T242	2		T259	9		T321	8
auto[0]	values[6]	values[5]	333	1			T6	22		T66	8		T125	16
auto[0]	values[6]	values[6]	105	1			T244	9		T265	12		T42	23
auto[0]	values[6]	values[7]	278	1			T58	2		T66	14		T61	14
auto[0]	values[7]	values[0]	220	1			T322	2		T40	8		T189	26
auto[0]	values[7]	values[1]	312	1			T323	6		T72	50		T189	36
auto[0]	values[7]	values[2]	413	1			T51	9		T273	8		T68	7
auto[0]	values[7]	values[3]	228	1			T236	7		T189	14		T169	8
auto[0]	values[7]	values[4]	374	1			T223	15		T324	12		T206	11
auto[0]	values[7]	values[5]	306	1			T325	20		T69	11		T239	21
auto[0]	values[7]	values[6]	334	1			T67	15		T223	13		T249	10
auto[0]	values[7]	values[7]	321	1			T211	4		T72	11		T239	11
auto[1]	values[0]	values[0]	261	1			T45	15		T34	6		T244	7
auto[1]	values[0]	values[1]	292	1			T206	7		T40	9		T271	46
auto[1]	values[0]	values[2]	161	1			T51	27		T68	7		T189	8
auto[1]	values[0]	values[3]	127	1			T51	12		T233	5		T234	7
auto[1]	values[0]	values[4]	136	1			T189	8		T301	6		T259	8
auto[1]	values[0]	values[5]	97	1			T17	4		T247	8		T326	10
auto[1]	values[0]	values[6]	202	1			T66	4		T41	7		T233	5
auto[1]	values[0]	values[7]	167	1			T240	16		T71	9		T248	11
auto[1]	values[1]	values[0]	140	1			T69	6		T41	7		T256	11
auto[1]	values[1]	values[1]	145	1			T189	10		T225	7		T327	8
auto[1]	values[1]	values[2]	283	1			T271	6		T233	12		T328	61
auto[1]	values[1]	values[3]	232	1			T236	12		T189	4		T42	15
auto[1]	values[1]	values[4]	235	1			T68	3		T290	16		T307	17
auto[1]	values[1]	values[5]	127	1			T45	30		T40	14		T329	7
auto[1]	values[1]	values[6]	279	1			T51	8		T61	9		T236	9
auto[1]	values[1]	values[7]	237	1			T61	63		T307	9		T234	14
auto[1]	values[2]	values[0]	199	1			T72	8		T189	9		T165	6
auto[1]	values[2]	values[1]	242	1			T68	4		T330	2		T239	10
auto[1]	values[2]	values[2]	265	1			T68	77		T236	24		T40	13
auto[1]	values[2]	values[3]	147	1			T206	6		T244	8		T252	7
auto[1]	values[2]	values[4]	164	1			T308	13		T42	11		T193	7
auto[1]	values[2]	values[5]	183	1			T66	12		T69	9		T70	18
auto[1]	values[2]	values[6]	239	1			T67	20		T206	17		T189	14
auto[1]	values[2]	values[7]	157	1			T70	11		T72	8		T206	11
auto[1]	values[3]	values[0]	241	1			T51	8		T69	12		T256	10
auto[1]	values[3]	values[1]	207	1			T51	10		T69	13		T40	11
auto[1]	values[3]	values[2]	192	1			T67	19		T206	9		T331	4
auto[1]	values[3]	values[3]	335	1			T236	10		T189	22		T293	18
auto[1]	values[3]	values[4]	163	1			T51	8		T332	8		T69	9
auto[1]	values[3]	values[5]	282	1			T69	13		T175	69		T247	45
auto[1]	values[3]	values[6]	296	1			T51	8		T61	10		T70	10
auto[1]	values[3]	values[7]	189	1			T51	4		T69	16		T244	9
auto[1]	values[4]	values[0]	139	1			T64	20		T72	4		T189	11
auto[1]	values[4]	values[1]	201	1			T206	9		T175	9		T253	11
auto[1]	values[4]	values[2]	268	1			T95	8		T70	15		T252	9
auto[1]	values[4]	values[3]	115	1			T51	9		T189	14		T252	7
auto[1]	values[4]	values[4]	167	1			T66	7		T69	9		T239	5
auto[1]	values[4]	values[5]	183	1			T10	16		T72	12		T232	6
auto[1]	values[4]	values[6]	313	1			T72	7		T333	14		T236	74
auto[1]	values[4]	values[7]	236	1			T45	11		T189	8		T334	10
auto[1]	values[5]	values[0]	212	1			T66	5		T34	16		T71	13
auto[1]	values[5]	values[1]	177	1			T63	6		T335	2		T193	10
auto[1]	values[5]	values[2]	241	1			T247	8		T264	10		T336	13
auto[1]	values[5]	values[3]	208	1			T239	3		T244	7		T252	7
auto[1]	values[5]	values[4]	312	1			T70	52		T248	9		T337	2
auto[1]	values[5]	values[5]	103	1			T45	15		T40	17		T189	9
auto[1]	values[5]	values[6]	145	1			T248	6		T252	4		T253	8
auto[1]	values[5]	values[7]	157	1			T51	24		T206	11		T328	11
auto[1]	values[6]	values[0]	163	1			T45	14		T67	4		T69	9
auto[1]	values[6]	values[1]	124	1			T72	11		T232	10		T225	8
auto[1]	values[6]	values[2]	149	1			T67	13		T69	5		T248	13
auto[1]	values[6]	values[3]	148	1			T202	8		T236	8		T41	13
auto[1]	values[6]	values[4]	158	1			T259	40		T338	13		T339	8
auto[1]	values[6]	values[5]	166	1			T66	12		T69	8		T236	13
auto[1]	values[6]	values[6]	109	1			T244	11		T265	12		T42	21
auto[1]	values[6]	values[7]	272	1			T66	6		T61	6		T70	5
auto[1]	values[7]	values[0]	209	1			T40	22		T189	14		T259	12
auto[1]	values[7]	values[1]	164	1			T72	11		T189	32		T232	7
auto[1]	values[7]	values[2]	180	1			T51	11		T68	13		T236	6
auto[1]	values[7]	values[3]	240	1			T236	13		T189	6		T41	9
auto[1]	values[7]	values[4]	232	1			T90	16		T223	28		T206	9
auto[1]	values[7]	values[5]	352	1			T69	9		T239	6		T262	7
auto[1]	values[7]	values[6]	488	1			T67	5		T223	32		T70	25
auto[1]	values[7]	values[7]	214	1			T72	16		T239	18		T41	11