Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	429	1			T45	3		T255	4		T51	4
auto[ReadAddrCrossIntoMailbox]	303	1			T45	2		T51	7		T66	1
auto[ReadAddrCrossOutOfMailbox]	343	1			T7	2		T45	2		T269	2
auto[ReadAddrCrossAllMailbox]	230	1			T45	2		T284	4		T66	2
auto[ReadAddrOutsideMailbox]	3867	1			T6	2		T8	2		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503

1

T6

1

T7

1

T8

1

auto[1]

2669

1

T6

1

T7

1

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	838	1			T6	2		T10	2		T45	8
read_ops[0x0b]	851	1			T9	2		T17	2		T55	2
read_ops[0x3b]	898	1			T10	4		T18	2		T60	2
read_ops[0x6b]	855	1			T10	2		T45	2		T284	4
read_ops[0xbb]	867	1			T8	2		T39	4		T45	1
read_ops[0xeb]	863	1			T7	2		T39	2		T136	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T45	1		T66	1		T69	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T45	1		T206	1		T236	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T51	1		T236	1		T189	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T51	1		T206	1		T236	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T45	2		T68	1		T301	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T341	1		T244	1		T252	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T45	1		T284	2		T66	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T45	1		T284	2		T69	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T6	1		T10	1		T45	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T6	1		T10	1		T45	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T51	1		T92	1		T272	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T66	1		T92	1		T272	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T51	2		T93	1		T236	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T93	1		T40	1		T342	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T269	1		T93	1		T69	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T269	1		T61	1		T93	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T236	1		T189	1		T252	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T68	1		T69	1		T234	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T9	1		T17	1		T55	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T9	1		T17	1		T55	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T255	2		T51	1		T92	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T255	2		T92	1		T71	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T67	2		T69	1		T72	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T51	1		T66	1		T232	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T68	1		T69	1		T206	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T206	1		T236	1		T233	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T273	1		T248	1		T236	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T273	1		T259	1		T343	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T10	2		T18	1		T60	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	349	1			T10	2		T18	1		T60	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T66	1		T285	1		T93	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	53	1			T285	1		T68	1		T93	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T93	2		T69	1		T289	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T45	1		T51	1		T61	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	40	1			T272	1		T69	2		T71	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T66	1		T272	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T272	2		T71	2		T72	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T67	1		T272	2		T72	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T10	1		T284	2		T51	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T10	1		T45	1		T284	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T67	1		T292	1		T239	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T51	1		T61	1		T292	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T51	1		T67	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T67	2		T68	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T223	1		T71	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T51	3		T69	1		T71	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T68	1		T93	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T68	1		T93	1		T344	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T8	1		T39	2		T45	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T8	1		T39	2		T228	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T297	1		T292	2		T239	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T45	1		T51	1		T61	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T45	1		T68	1		T72	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T67	1		T69	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T7	1		T51	1		T93	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T7	1		T93	2		T244	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T66	1		T272	2		T69	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T272	2		T69	1		T206	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T39	1		T136	1		T59	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T39	1		T136	1		T59	1