Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3644	1			T10	16		T63	6		T55	12
values[1]	3861	1			T7	2		T45	96		T50	12
values[2]	4138	1			T8	2		T9	6		T17	4
values[3]	4718	1			T136	6		T58	2		T45	20
values[4]	3598	1			T6	22		T13	10		T45	20
values[5]	4072	1			T57	16		T228	12		T284	12
values[6]	3572	1			T39	8		T60	14		T210	6
values[7]	4747	1			T18	22		T51	20		T211	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3596	1			T45	40		T66	40		T305	14
values[1]	3679	1			T6	22		T45	29		T75	4
values[2]	4239	1			T7	2		T17	4		T57	16
values[3]	3791	1			T13	10		T39	8		T56	8
values[4]	4154	1			T136	6		T45	126		T209	4
values[5]	4743	1			T10	16		T59	6		T269	2
values[6]	4290	1			T18	22		T63	6		T55	12
values[7]	3858	1			T8	2		T9	6		T58	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31539

1

T6

22

T7

2

T8

2

auto[1]

811

1

T45

7

T64

8

T51

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	484	1			T67	46		T69	40		T206	20
auto[0]	values[0]	values[1]	297	1			T45	28		T40	20		T234	55
auto[0]	values[0]	values[2]	439	1			T257	20		T345	20		T320	12
auto[0]	values[0]	values[3]	319	1			T56	8		T311	2		T223	43
auto[0]	values[0]	values[4]	389	1			T51	20		T290	16		T239	20
auto[0]	values[0]	values[5]	662	1			T10	16		T70	20		T72	60
auto[0]	values[0]	values[6]	398	1			T63	6		T55	12		T70	35
auto[0]	values[0]	values[7]	562	1			T51	19		T69	20		T41	63
auto[0]	values[1]	values[0]	268	1			T69	37		T312	10		T252	20
auto[0]	values[1]	values[1]	417	1			T273	8		T236	19		T127	18
auto[0]	values[1]	values[2]	537	1			T7	2		T51	20		T61	95
auto[0]	values[1]	values[3]	527	1			T50	12		T310	8		T242	2
auto[0]	values[1]	values[4]	333	1			T45	93		T233	20		T254	17
auto[0]	values[1]	values[5]	733	1			T304	18		T71	19		T189	29
auto[0]	values[1]	values[6]	587	1			T292	10		T69	17		T346	12
auto[0]	values[1]	values[7]	349	1			T62	22		T206	20		T40	32
auto[0]	values[2]	values[0]	558	1			T45	40		T72	20		T189	18
auto[0]	values[2]	values[1]	680	1			T66	20		T313	2		T70	29
auto[0]	values[2]	values[2]	425	1			T17	4		T69	17		T72	45
auto[0]	values[2]	values[3]	422	1			T282	26		T189	19		T41	22
auto[0]	values[2]	values[4]	483	1			T45	30		T66	16		T316	20
auto[0]	values[2]	values[5]	420	1			T59	6		T272	16		T332	8
auto[0]	values[2]	values[6]	680	1			T34	23		T249	10		T175	75
auto[0]	values[2]	values[7]	373	1			T8	2		T9	6		T70	22
auto[0]	values[3]	values[0]	579	1			T66	39		T305	14		T40	18
auto[0]	values[3]	values[1]	619	1			T75	4		T51	20		T267	12
auto[0]	values[3]	values[2]	461	1			T45	19		T347	10		T328	35
auto[0]	values[3]	values[3]	567	1			T255	18		T68	43		T34	20
auto[0]	values[3]	values[4]	657	1			T136	6		T209	4		T68	20
auto[0]	values[3]	values[5]	584	1			T125	16		T175	18		T248	20
auto[0]	values[3]	values[6]	462	1			T51	44		T285	2		T268	24
auto[0]	values[3]	values[7]	674	1			T58	2		T95	8		T223	45
auto[0]	values[4]	values[0]	550	1			T297	10		T323	6		T206	20
auto[0]	values[4]	values[1]	495	1			T6	22		T51	40		T276	14
auto[0]	values[4]	values[2]	390	1			T286	10		T206	17		T247	20
auto[0]	values[4]	values[3]	172	1			T13	10		T306	26		T69	18
auto[0]	values[4]	values[4]	280	1			T299	14		T52	12		T69	19
auto[0]	values[4]	values[5]	477	1			T64	12		T205	46		T90	16
auto[0]	values[4]	values[6]	479	1			T45	18		T69	20		T232	20
auto[0]	values[4]	values[7]	637	1			T51	26		T67	26		T93	20
auto[0]	values[5]	values[0]	294	1			T68	20		T348	20		T239	27
auto[0]	values[5]	values[1]	474	1			T100	4		T248	18		T244	19
auto[0]	values[5]	values[2]	665	1			T57	16		T239	21		T166	8
auto[0]	values[5]	values[3]	547	1			T51	23		T68	18		T206	20
auto[0]	values[5]	values[4]	593	1			T228	12		T67	20		T236	62
auto[0]	values[5]	values[5]	498	1			T269	2		T236	20		T189	40
auto[0]	values[5]	values[6]	421	1			T61	20		T298	14		T349	6
auto[0]	values[5]	values[7]	492	1			T284	12		T325	20		T206	17
auto[0]	values[6]	values[0]	359	1			T67	20		T69	20		T244	20
auto[0]	values[6]	values[1]	311	1			T210	6		T275	12		T189	51
auto[0]	values[6]	values[2]	273	1			T51	42		T247	23		T308	30
auto[0]	values[6]	values[3]	486	1			T39	8		T236	19		T41	52
auto[0]	values[6]	values[4]	657	1			T69	20		T70	67		T72	20
auto[0]	values[6]	values[5]	559	1			T324	12		T237	14		T329	20
auto[0]	values[6]	values[6]	443	1			T303	4		T71	20		T189	62
auto[0]	values[6]	values[7]	402	1			T60	14		T70	20		T318	4
auto[0]	values[7]	values[0]	416	1			T92	6		T281	6		T308	22
auto[0]	values[7]	values[1]	297	1			T69	18		T202	8		T72	18
auto[0]	values[7]	values[2]	936	1			T65	45		T266	20		T248	23
auto[0]	values[7]	values[3]	665	1			T66	40		T68	89		T70	28
auto[0]	values[7]	values[4]	646	1			T69	18		T340	18		T240	16
auto[0]	values[7]	values[5]	689	1			T51	20		T211	4		T236	66
auto[0]	values[7]	values[6]	703	1			T18	22		T61	20		T236	88
auto[0]	values[7]	values[7]	288	1			T189	27		T230	6		T234	20
auto[1]	values[0]	values[0]	9	1			T67	1		T328	1		T350	1
auto[1]	values[0]	values[1]	12	1			T45	1		T234	3		T288	3
auto[1]	values[0]	values[2]	10	1			T351	3		T352	1		T172	2
auto[1]	values[0]	values[3]	5	1			T40	2		T254	1		T334	1
auto[1]	values[0]	values[4]	20	1			T244	4		T353	6		T354	1
auto[1]	values[0]	values[5]	16	1			T72	1		T244	4		T328	3
auto[1]	values[0]	values[6]	10	1			T253	2		T261	2		T355	1
auto[1]	values[0]	values[7]	12	1			T51	1		T41	4		T356	2
auto[1]	values[1]	values[0]	14	1			T69	3		T265	4		T357	3
auto[1]	values[1]	values[1]	4	1			T236	1		T308	2		T358	1
auto[1]	values[1]	values[2]	17	1			T328	1		T359	2		T360	2
auto[1]	values[1]	values[3]	10	1			T259	1		T225	2		T361	4
auto[1]	values[1]	values[4]	13	1			T45	3		T254	3		T339	1
auto[1]	values[1]	values[5]	17	1			T71	1		T189	2		T42	1
auto[1]	values[1]	values[6]	27	1			T69	3		T346	4		T238	1
auto[1]	values[1]	values[7]	8	1			T42	2		T336	1		T229	1
auto[1]	values[2]	values[0]	12	1			T189	2		T252	1		T247	1
auto[1]	values[2]	values[1]	14	1			T72	2		T41	2		T256	1
auto[1]	values[2]	values[2]	15	1			T69	3		T72	1		T42	2
auto[1]	values[2]	values[3]	6	1			T189	1		T362	1		T194	3
auto[1]	values[2]	values[4]	13	1			T66	4		T244	1		T252	1
auto[1]	values[2]	values[5]	7	1			T253	3		T261	2		T363	1
auto[1]	values[2]	values[6]	25	1			T175	1		T253	2		T334	1
auto[1]	values[2]	values[7]	5	1			T70	1		T40	1		T247	3
auto[1]	values[3]	values[0]	12	1			T66	1		T40	2		T259	1
auto[1]	values[3]	values[1]	11	1			T256	2		T225	1		T364	1
auto[1]	values[3]	values[2]	10	1			T45	1		T362	1		T365	2
auto[1]	values[3]	values[3]	15	1			T68	2		T328	1		T365	1
auto[1]	values[3]	values[4]	20	1			T239	3		T259	3		T252	3
auto[1]	values[3]	values[5]	18	1			T175	2		T248	2		T189	3
auto[1]	values[3]	values[6]	11	1			T51	2		T72	4		T261	1
auto[1]	values[3]	values[7]	18	1			T265	2		T263	6		T308	3
auto[1]	values[4]	values[0]	19	1			T175	2		T189	1		T343	3
auto[1]	values[4]	values[1]	12	1			T259	2		T343	3		T193	2
auto[1]	values[4]	values[2]	5	1			T206	3		T262	1		T366	1
auto[1]	values[4]	values[3]	6	1			T69	2		T367	2		T352	2
auto[1]	values[4]	values[4]	8	1			T69	1		T236	1		T368	1
auto[1]	values[4]	values[5]	23	1			T64	8		T40	3		T244	1
auto[1]	values[4]	values[6]	20	1			T45	2		T244	1		T336	1
auto[1]	values[4]	values[7]	25	1			T51	2		T67	1		T40	4
auto[1]	values[5]	values[0]	4	1			T334	1		T369	1		T87	2
auto[1]	values[5]	values[1]	17	1			T248	2		T244	1		T234	2
auto[1]	values[5]	values[2]	19	1			T252	2		T307	1		T256	1
auto[1]	values[5]	values[3]	8	1			T68	2		T232	1		T256	1
auto[1]	values[5]	values[4]	16	1			T236	2		T40	4		T271	1
auto[1]	values[5]	values[5]	13	1			T189	1		T225	4		T262	4
auto[1]	values[5]	values[6]	6	1			T370	1		T371	2		T372	3
auto[1]	values[5]	values[7]	5	1			T206	3		T338	1		T373	1
auto[1]	values[6]	values[0]	12	1			T367	1		T170	1		T370	2
auto[1]	values[6]	values[1]	8	1			T247	3		T374	1		T375	1
auto[1]	values[6]	values[2]	14	1			T247	3		T343	2		T288	1
auto[1]	values[6]	values[3]	12	1			T236	1		T41	2		T244	2
auto[1]	values[6]	values[4]	11	1			T248	1		T247	1		T225	1
auto[1]	values[6]	values[5]	10	1			T232	1		T252	1		T376	1
auto[1]	values[6]	values[6]	8	1			T189	1		T232	1		T42	1
auto[1]	values[6]	values[7]	7	1			T189	2		T252	1		T364	1
auto[1]	values[7]	values[0]	6	1			T359	1		T336	2		T377	2
auto[1]	values[7]	values[1]	11	1			T69	2		T72	2		T259	1
auto[1]	values[7]	values[2]	23	1			T248	1		T42	1		T225	1
auto[1]	values[7]	values[3]	24	1			T68	4		T244	1		T247	1
auto[1]	values[7]	values[4]	15	1			T69	2		T41	3		T232	1
auto[1]	values[7]	values[5]	17	1			T271	1		T256	1		T261	1
auto[1]	values[7]	values[6]	10	1			T236	1		T232	1		T378	3
auto[1]	values[7]	values[7]	1	1			T379	1		-	-		-	-