Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	721	1			T34	7		T35	10		T37	10
all_values[1]	721	1			T34	7		T35	10		T37	10
all_values[2]	721	1			T34	7		T35	10		T37	10
all_values[3]	721	1			T34	7		T35	10		T37	10
all_values[4]	721	1			T34	7		T35	10		T37	10
all_values[5]	721	1			T34	7		T35	10		T37	10
all_values[6]	721	1			T34	7		T35	10		T37	10
all_values[7]	721	1			T34	7		T35	10		T37	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2999

1

T34

24

T35

30

T37

45

auto[1]

2769

1

T34

32

T35

50

T37

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2192

1

T34

20

T35

33

T37

23

auto[1]

3576

1

T34

36

T35

47

T37

57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3238

1

T34

28

T35

42

T37

44

auto[1]

2530

1

T34

28

T35

38

T37

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	143	1			T34	1		T37	1		T175	3
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T34	2		T37	2		T175	4
all_values[0]	auto[0]	auto[1]	auto[0]	121	1			T35	3		T175	5		T40	7
all_values[0]	auto[0]	auto[1]	auto[1]	69	1			T35	1		T37	2		T175	3
all_values[0]	auto[1]	auto[0]	auto[1]	160	1			T34	3		T35	3		T37	2
all_values[0]	auto[1]	auto[1]	auto[1]	156	1			T34	1		T35	3		T37	3
all_values[1]	auto[0]	auto[0]	auto[0]	142	1			T34	2		T37	3		T175	4
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T34	1		T37	1		T175	3
all_values[1]	auto[0]	auto[1]	auto[0]	116	1			T34	1		T35	3		T175	2
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T35	4		T37	2		T175	2
all_values[1]	auto[1]	auto[0]	auto[1]	159	1			T34	2		T37	2		T175	9
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T34	1		T35	3		T37	2
all_values[2]	auto[0]	auto[0]	auto[0]	149	1			T34	1		T35	2		T37	3
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T37	1		T40	3		T189	3
all_values[2]	auto[0]	auto[1]	auto[0]	118	1			T34	2		T35	1		T37	1
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T37	2		T175	2		T40	1
all_values[2]	auto[1]	auto[0]	auto[1]	155	1			T34	2		T35	5		T37	1
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T34	2		T35	2		T37	2
all_values[3]	auto[0]	auto[0]	auto[0]	138	1			T35	3		T37	2		T175	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T35	1		T37	1		T175	5
all_values[3]	auto[0]	auto[1]	auto[0]	119	1			T34	1		T35	2		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T37	2		T175	2		T41	1
all_values[3]	auto[1]	auto[0]	auto[1]	165	1			T34	1		T35	1		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T34	5		T35	3		T37	3
all_values[4]	auto[0]	auto[0]	auto[0]	119	1			T35	2		T175	9		T40	5
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T35	1		T37	1		T175	1
all_values[4]	auto[0]	auto[1]	auto[0]	142	1			T34	3		T35	1		T37	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T34	1		T35	1		T37	2
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T34	2		T35	2		T37	4
all_values[4]	auto[1]	auto[1]	auto[1]	142	1			T34	1		T35	3		T37	2
all_values[5]	auto[0]	auto[0]	auto[0]	209	1			T34	1		T35	4		T37	6
all_values[5]	auto[0]	auto[1]	auto[0]	195	1			T34	5		T35	4		T175	6
all_values[5]	auto[1]	auto[0]	auto[1]	160	1			T37	2		T175	8		T40	2
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T34	1		T35	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	125	1			T34	2		T35	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T34	1		T37	2		T175	3
all_values[6]	auto[0]	auto[1]	auto[0]	116	1			T35	2		T37	1		T175	5
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T34	1		T175	2		T40	1
all_values[6]	auto[1]	auto[0]	auto[1]	175	1			T34	2		T35	3		T37	4
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T34	1		T35	3		T37	1
all_values[7]	auto[0]	auto[0]	auto[0]	148	1			T35	1		T175	1		T40	7
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T34	1		T37	2		T175	2
all_values[7]	auto[0]	auto[1]	auto[0]	92	1			T34	1		T35	3		T37	2
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T34	1		T35	1		T37	1
all_values[7]	auto[1]	auto[0]	auto[1]	165	1			T37	2		T175	4		T189	4
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T34	4		T35	5		T37	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal