Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1689

1

T11

19

T25

2

T26

11

auto[1]

1612

1

T11

14

T25

1

T26

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1726

1

T28

11

T46

2

T77

16

auto[1]

1575

1

T11

33

T25

3

T26

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2661

1

T11

33

T25

3

T26

17

auto[1]

640

1

T28

2

T46

2

T77

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	663	1			T11	9		T25	2		T26	4
valid[1]	669	1			T11	5		T26	4		T28	3
valid[2]	703	1			T11	2		T26	2		T30	3
valid[3]	623	1			T11	9		T26	2		T28	2
valid[4]	643	1			T11	8		T25	1		T26	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	106	1			T28	1		T77	2		T79	1
auto[0]	auto[0]	valid[0]	auto[1]	183	1			T11	7		T25	2		T26	3
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T28	1		T77	1		T401	1
auto[0]	auto[0]	valid[1]	auto[1]	142	1			T11	1		T26	2		T30	1
auto[0]	auto[0]	valid[2]	auto[0]	122	1			T77	2		T80	1		T118	1
auto[0]	auto[0]	valid[2]	auto[1]	187	1			T11	1		T30	1		T76	1
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T77	1		T99	1		T67	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T11	6		T26	1		T76	2
auto[0]	auto[0]	valid[4]	auto[0]	125	1			T77	2		T401	1		T121	1
auto[0]	auto[0]	valid[4]	auto[1]	143	1			T11	4		T26	5		T30	2
auto[0]	auto[1]	valid[0]	auto[0]	108	1			T28	2		T77	1		T80	1
auto[0]	auto[1]	valid[0]	auto[1]	138	1			T11	2		T26	1		T32	1
auto[0]	auto[1]	valid[1]	auto[0]	131	1			T28	1		T77	1		T80	1
auto[0]	auto[1]	valid[1]	auto[1]	161	1			T11	4		T26	2		T81	1
auto[0]	auto[1]	valid[2]	auto[0]	95	1			T77	1		T34	1		T411	1
auto[0]	auto[1]	valid[2]	auto[1]	167	1			T11	1		T26	2		T30	2
auto[0]	auto[1]	valid[3]	auto[0]	103	1			T28	2		T77	1		T79	1
auto[0]	auto[1]	valid[3]	auto[1]	140	1			T11	3		T26	1		T30	1
auto[0]	auto[1]	valid[4]	auto[0]	88	1			T28	2		T80	2		T250	1
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T11	4		T25	1		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	60	1			T79	1		T80	1		T401	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T79	1		T80	1		T67	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T46	1		T118	1		T51	1
auto[1]	auto[0]	valid[3]	auto[0]	56	1			T35	1		T37	1		T400	1
auto[1]	auto[0]	valid[4]	auto[0]	62	1			T28	1		T46	1		T77	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T77	1		T99	1		T121	1
auto[1]	auto[1]	valid[1]	auto[0]	51	1			T28	1		T80	1		T51	1
auto[1]	auto[1]	valid[2]	auto[0]	63	1			T77	1		T118	2		T51	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T118	1		T99	1		T250	1
auto[1]	auto[1]	valid[4]	auto[0]	59	1			T77	1		T80	1		T118	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal