Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45314

1

T4

9

T5

46

T27

13

auto[1]

15616

1

T11

285

T25

3

T26

175

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44370

1

T4

4

T5

25

T11

285

auto[1]

16560

1

T4

5

T5

21

T27

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31411	1			T4	6		T5	21		T11	145
others[1]	5185	1			T4	2		T5	4		T11	22
others[2]	5148	1			T4	1		T5	6		T11	25
others[3]	5753	1			T5	5		T11	24		T26	22
interest[1]	3333	1			T5	2		T11	14		T26	9
interest[4]	20590	1			T4	4		T5	13		T11	103
interest[64]	10100	1			T5	8		T11	55		T26	30

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14676	1			T4	3		T5	13		T27	1
auto[0]	auto[0]	others[1]	2434	1			T4	1		T5	1		T27	3
auto[0]	auto[0]	others[2]	2432	1			T5	3		T27	2		T28	8
auto[0]	auto[0]	others[3]	2783	1			T5	3		T28	11		T31	1
auto[0]	auto[0]	interest[1]	1658	1			T5	1		T28	6		T46	1
auto[0]	auto[0]	interest[4]	9518	1			T4	3		T5	8		T28	50
auto[0]	auto[0]	interest[64]	4771	1			T5	4		T27	2		T28	25
auto[0]	auto[1]	others[0]	8149	1			T11	145		T25	3		T26	79
auto[0]	auto[1]	others[1]	1345	1			T11	22		T26	14		T31	2
auto[0]	auto[1]	others[2]	1319	1			T11	25		T26	21		T81	19
auto[0]	auto[1]	others[3]	1414	1			T11	24		T26	22		T31	1
auto[0]	auto[1]	interest[1]	805	1			T11	14		T26	9		T31	1
auto[0]	auto[1]	interest[4]	5466	1			T11	103		T25	3		T26	48
auto[0]	auto[1]	interest[64]	2584	1			T11	55		T26	30		T31	3
auto[1]	auto[0]	others[0]	8586	1			T4	3		T5	8		T27	3
auto[1]	auto[0]	others[1]	1406	1			T4	1		T5	3		T28	7
auto[1]	auto[0]	others[2]	1397	1			T4	1		T5	3		T27	2
auto[1]	auto[0]	others[3]	1556	1			T5	2		T28	5		T46	1
auto[1]	auto[0]	interest[1]	870	1			T5	1		T28	3		T31	1
auto[1]	auto[0]	interest[4]	5606	1			T4	1		T5	5		T27	3
auto[1]	auto[0]	interest[64]	2745	1			T5	4		T28	15		T31	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal