Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 1 4 80.00
Crosses 6 2 4 66.67


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 2 4 66.67 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] 78518 1 T3 8 T5 515 T6 6
auto[PassthroughMode] 54474 1 T4 2 T7 26 T8 16



Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 30353 1 T4 2 T7 26 T8 16
auto[1] 102639 1 T3 8 T5 515 T6 6



Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 2 4 66.67 2


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Covered bins
cp_mode   cp_tpm_enabled   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] auto[0] 13764 1 T10 1 T60 4 T38 20
auto[FlashMode] auto[1] 64754 1 T3 8 T5 515 T6 6
auto[PassthroughMode] auto[0] 16589 1 T4 2 T7 26 T8 16
auto[PassthroughMode] auto[1] 37885 1 T78 305 T47 525 T58 643