Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2710782	1			T1	1		T2	1		T3	1
all_pins[1]	2710782	1			T1	1		T2	1		T3	1
all_pins[2]	2710782	1			T1	1		T2	1		T3	1
all_pins[3]	2710782	1			T1	1		T2	1		T3	1
all_pins[4]	2710782	1			T1	1		T2	1		T3	1
all_pins[5]	2710782	1			T1	1		T2	1		T3	1
all_pins[6]	2710782	1			T1	1		T2	1		T3	1
all_pins[7]	2710782	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21635921	1			T1	8		T2	8		T3	8
values[0x1]	50335	1			T21	30		T87	36		T33	28
transitions[0x0=>0x1]	49304	1			T21	17		T87	23		T33	22
transitions[0x1=>0x0]	49315	1			T21	17		T87	23		T33	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2710363	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	419	1			T21	3		T87	6		T33	2
all_pins[0]	transitions[0x0=>0x1]	175	1			T21	1		T87	4		T167	39
all_pins[0]	transitions[0x1=>0x0]	309	1			T21	3		T87	3		T33	4
all_pins[1]	values[0x0]	2710229	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	553	1			T21	5		T87	5		T33	6
all_pins[1]	transitions[0x0=>0x1]	348	1			T21	2		T87	4		T33	4
all_pins[1]	transitions[0x1=>0x0]	247	1			T21	2		T87	6		T33	3
all_pins[2]	values[0x0]	2710330	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	452	1			T21	5		T87	7		T33	5
all_pins[2]	transitions[0x0=>0x1]	389	1			T21	2		T87	2		T33	3
all_pins[2]	transitions[0x1=>0x0]	131	1			T21	1		T87	2		T33	2
all_pins[3]	values[0x0]	2710588	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	194	1			T21	4		T87	7		T33	4
all_pins[3]	transitions[0x0=>0x1]	141	1			T21	2		T87	5		T33	4
all_pins[3]	transitions[0x1=>0x0]	157	1			T21	1		T87	2		T33	2
all_pins[4]	values[0x0]	2710572	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	210	1			T21	3		T87	4		T33	2
all_pins[4]	transitions[0x0=>0x1]	166	1			T21	2		T87	3		T33	2
all_pins[4]	transitions[0x1=>0x0]	403	1			T21	5		T87	3		T33	3
all_pins[5]	values[0x0]	2710335	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	447	1			T21	6		T87	4		T33	3
all_pins[5]	transitions[0x0=>0x1]	128	1			T21	5		T87	3		T33	3
all_pins[5]	transitions[0x1=>0x0]	47543	1			T21	1		T87	1		T33	1
all_pins[6]	values[0x0]	2662920	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	47862	1			T21	2		T87	2		T33	1
all_pins[6]	transitions[0x0=>0x1]	47809	1			T21	2		T87	1		T33	1
all_pins[6]	transitions[0x1=>0x0]	145	1			T21	2		T33	5		T167	4
all_pins[7]	values[0x0]	2710584	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	198	1			T21	2		T87	1		T33	5
all_pins[7]	transitions[0x0=>0x1]	148	1			T21	1		T87	1		T33	5
all_pins[7]	transitions[0x1=>0x0]	380	1			T21	2		T87	6		T33	2