Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18086

1

T7

12

T11

2

T13

41

auto[1]

13640

1

T8

12

T49

14

T43

57

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4181	1			T112	4		T80	20		T52	16
values[1]	3878	1			T43	60		T109	14		T78	20
values[2]	3576	1			T11	2		T61	6		T51	18
values[3]	4106	1			T7	12		T8	12		T55	60
values[4]	3859	1			T55	40		T56	12		T47	20
values[5]	3770	1			T17	8		T18	6		T49	14
values[6]	4219	1			T13	41		T19	10		T36	76
values[7]	4137	1			T43	20		T50	25		T54	116

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3376	1			T43	20		T79	4		T124	6
values[1]	3860	1			T17	8		T43	20		T109	14
values[2]	4025	1			T36	76		T43	20		T51	18
values[3]	4978	1			T19	10		T43	40		T195	10
values[4]	4351	1			T8	12		T11	2		T43	20
values[5]	3916	1			T7	12		T112	4		T50	25
values[6]	3512	1			T43	20		T61	6		T78	20
values[7]	3708	1			T13	41		T18	6		T49	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	234	1			T124	6		T55	14		T101	11
auto[0]	values[0]	values[1]	209	1			T54	12		T33	9		T264	12
auto[0]	values[0]	values[2]	253	1			T204	12		T253	16		T193	15
auto[0]	values[0]	values[3]	309	1			T209	10		T216	14		T102	24
auto[0]	values[0]	values[4]	414	1			T204	48		T33	9		T251	4
auto[0]	values[0]	values[5]	407	1			T112	4		T46	10		T32	80
auto[0]	values[0]	values[6]	286	1			T224	22		T176	8		T210	8
auto[0]	values[0]	values[7]	208	1			T80	20		T55	12		T47	11
auto[0]	values[1]	values[0]	237	1			T244	16		T204	12		T265	26
auto[0]	values[1]	values[1]	298	1			T43	9		T109	14		T147	7
auto[0]	values[1]	values[2]	360	1			T43	12		T177	35		T266	10
auto[0]	values[1]	values[3]	501	1			T57	33		T254	6		T74	16
auto[0]	values[1]	values[4]	444	1			T43	17		T258	4		T147	15
auto[0]	values[1]	values[5]	208	1			T175	14		T267	2		T209	12
auto[0]	values[1]	values[6]	163	1			T78	14		T210	13		T203	11
auto[0]	values[1]	values[7]	161	1			T55	29		T193	14		T233	10
auto[0]	values[2]	values[0]	115	1			T176	13		T219	16		T196	12
auto[0]	values[2]	values[1]	250	1			T219	23		T234	13		T149	7
auto[0]	values[2]	values[2]	299	1			T47	8		T209	11		T71	10
auto[0]	values[2]	values[3]	344	1			T268	4		T176	58		T246	7
auto[0]	values[2]	values[4]	324	1			T11	2		T47	13		T57	12
auto[0]	values[2]	values[5]	137	1			T259	6		T213	9		T216	7
auto[0]	values[2]	values[6]	220	1			T61	6		T54	13		T269	10
auto[0]	values[2]	values[7]	263	1			T54	14		T177	9		T193	15
auto[0]	values[3]	values[0]	250	1			T55	10		T33	10		T176	8
auto[0]	values[3]	values[1]	309	1			T47	89		T270	14		T75	12
auto[0]	values[3]	values[2]	220	1			T54	17		T221	15		T147	10
auto[0]	values[3]	values[3]	402	1			T57	12		T204	37		T233	8
auto[0]	values[3]	values[4]	297	1			T55	23		T177	10		T233	9
auto[0]	values[3]	values[5]	214	1			T7	12		T75	11		T216	11
auto[0]	values[3]	values[6]	168	1			T271	12		T272	11		T202	12
auto[0]	values[3]	values[7]	365	1			T54	33		T245	6		T233	14
auto[0]	values[4]	values[0]	253	1			T55	6		T99	20		T74	12
auto[0]	values[4]	values[1]	262	1			T58	9		T204	11		T209	8
auto[0]	values[4]	values[2]	265	1			T209	11		T273	2		T225	15
auto[0]	values[4]	values[3]	452	1			T47	10		T177	82		T204	13
auto[0]	values[4]	values[4]	148	1			T55	11		T57	11		T58	5
auto[0]	values[4]	values[5]	251	1			T246	12		T271	13		T272	9
auto[0]	values[4]	values[6]	300	1			T241	6		T274	4		T75	8
auto[0]	values[4]	values[7]	235	1			T101	12		T256	67		T210	14
auto[0]	values[5]	values[0]	321	1			T79	4		T221	8		T32	13
auto[0]	values[5]	values[1]	331	1			T17	8		T54	13		T177	8
auto[0]	values[5]	values[2]	269	1			T223	6		T58	16		T175	9
auto[0]	values[5]	values[3]	201	1			T43	9		T78	15		T39	11
auto[0]	values[5]	values[4]	176	1			T47	12		T58	11		T242	8
auto[0]	values[5]	values[5]	322	1			T47	90		T57	8		T33	13
auto[0]	values[5]	values[6]	270	1			T43	11		T47	10		T275	6
auto[0]	values[5]	values[7]	250	1			T18	6		T175	99		T177	12
auto[0]	values[6]	values[0]	243	1			T221	10		T193	10		T213	10
auto[0]	values[6]	values[1]	338	1			T233	62		T263	12		T227	89
auto[0]	values[6]	values[2]	292	1			T36	76		T233	14		T276	10
auto[0]	values[6]	values[3]	464	1			T19	10		T43	11		T195	10
auto[0]	values[6]	values[4]	179	1			T53	36		T47	6		T193	15
auto[0]	values[6]	values[5]	307	1			T75	21		T149	11		T277	28
auto[0]	values[6]	values[6]	246	1			T55	12		T58	9		T176	40
auto[0]	values[6]	values[7]	395	1			T13	41		T54	10		T198	10
auto[0]	values[7]	values[0]	231	1			T43	14		T239	8		T71	8
auto[0]	values[7]	values[1]	297	1			T175	62		T33	12		T218	18
auto[0]	values[7]	values[2]	321	1			T54	18		T57	17		T175	12
auto[0]	values[7]	values[3]	360	1			T33	14		T176	11		T278	22
auto[0]	values[7]	values[4]	317	1			T175	12		T246	12		T241	25
auto[0]	values[7]	values[5]	466	1			T50	25		T54	7		T144	8
auto[0]	values[7]	values[6]	310	1			T57	13		T58	12		T257	24
auto[0]	values[7]	values[7]	145	1			T54	10		T279	6		T71	21
auto[1]	values[0]	values[0]	144	1			T55	6		T101	9		T71	7
auto[1]	values[0]	values[1]	215	1			T54	71		T33	11		T241	5
auto[1]	values[0]	values[2]	196	1			T204	46		T193	5		T178	7
auto[1]	values[0]	values[3]	302	1			T209	119		T216	6		T149	13
auto[1]	values[0]	values[4]	307	1			T204	11		T33	11		T213	6
auto[1]	values[0]	values[5]	397	1			T32	5		T252	20		T101	9
auto[1]	values[0]	values[6]	169	1			T176	12		T210	12		T280	8
auto[1]	values[0]	values[7]	131	1			T52	16		T55	8		T47	35
auto[1]	values[1]	values[0]	144	1			T204	8		T246	17		T71	22
auto[1]	values[1]	values[1]	204	1			T43	11		T147	13		T33	6
auto[1]	values[1]	values[2]	180	1			T43	8		T177	6		T219	10
auto[1]	values[1]	values[3]	189	1			T57	6		T74	6		T219	3
auto[1]	values[1]	values[4]	239	1			T43	3		T147	7		T177	8
auto[1]	values[1]	values[5]	229	1			T175	6		T209	8		T74	6
auto[1]	values[1]	values[6]	206	1			T78	6		T210	7		T203	78
auto[1]	values[1]	values[7]	115	1			T55	11		T193	6		T233	10
auto[1]	values[2]	values[0]	76	1			T176	29		T219	4		T281	8
auto[1]	values[2]	values[1]	230	1			T282	22		T219	17		T234	7
auto[1]	values[2]	values[2]	197	1			T51	18		T47	17		T209	29
auto[1]	values[2]	values[3]	147	1			T176	8		T246	13		T149	6
auto[1]	values[2]	values[4]	338	1			T47	7		T57	15		T33	7
auto[1]	values[2]	values[5]	142	1			T213	44		T216	13		T283	11
auto[1]	values[2]	values[6]	121	1			T54	7		T71	24		T227	5
auto[1]	values[2]	values[7]	373	1			T54	60		T177	27		T193	5
auto[1]	values[3]	values[0]	143	1			T55	10		T33	24		T176	12
auto[1]	values[3]	values[1]	127	1			T47	4		T75	8		T227	4
auto[1]	values[3]	values[2]	232	1			T54	3		T221	5		T147	10
auto[1]	values[3]	values[3]	214	1			T57	8		T204	8		T233	12
auto[1]	values[3]	values[4]	351	1			T8	12		T55	17		T177	10
auto[1]	values[3]	values[5]	192	1			T75	9		T216	9		T227	8
auto[1]	values[3]	values[6]	242	1			T271	8		T272	9		T202	8
auto[1]	values[3]	values[7]	380	1			T54	7		T233	16		T246	6
auto[1]	values[4]	values[0]	270	1			T55	14		T56	12		T74	11
auto[1]	values[4]	values[1]	271	1			T58	15		T204	68		T209	16
auto[1]	values[4]	values[2]	260	1			T209	9		T225	12		T234	27
auto[1]	values[4]	values[3]	294	1			T47	10		T177	7		T204	7
auto[1]	values[4]	values[4]	130	1			T55	9		T57	9		T58	40
auto[1]	values[4]	values[5]	153	1			T246	10		T271	7		T272	11
auto[1]	values[4]	values[6]	221	1			T241	34		T75	17		T234	9
auto[1]	values[4]	values[7]	94	1			T101	8		T210	6		T284	14
auto[1]	values[5]	values[0]	242	1			T221	12		T32	7		T246	12
auto[1]	values[5]	values[1]	219	1			T54	7		T177	35		T33	8
auto[1]	values[5]	values[2]	214	1			T58	8		T175	11		T246	10
auto[1]	values[5]	values[3]	182	1			T43	11		T78	9		T39	10
auto[1]	values[5]	values[4]	144	1			T47	31		T58	9		T71	10
auto[1]	values[5]	values[5]	184	1			T47	7		T57	12		T285	2
auto[1]	values[5]	values[6]	274	1			T43	9		T47	10		T241	78
auto[1]	values[5]	values[7]	171	1			T49	14		T175	5		T177	8
auto[1]	values[6]	values[0]	247	1			T221	10		T193	10		T286	4
auto[1]	values[6]	values[1]	135	1			T233	34		T227	7		T287	9
auto[1]	values[6]	values[2]	192	1			T233	6		T227	7		T238	7
auto[1]	values[6]	values[3]	230	1			T43	9		T147	7		T175	13
auto[1]	values[6]	values[4]	345	1			T47	14		T193	5		T233	7
auto[1]	values[6]	values[5]	180	1			T59	22		T75	6		T149	9
auto[1]	values[6]	values[6]	195	1			T55	8		T58	23		T248	16
auto[1]	values[6]	values[7]	231	1			T54	10		T288	4		T74	5
auto[1]	values[7]	values[0]	226	1			T43	6		T71	12		T227	11
auto[1]	values[7]	values[1]	165	1			T175	14		T33	18		T66	7
auto[1]	values[7]	values[2]	275	1			T54	2		T57	24		T175	90
auto[1]	values[7]	values[3]	387	1			T33	11		T176	52		T193	11
auto[1]	values[7]	values[4]	198	1			T175	8		T246	8		T241	64
auto[1]	values[7]	values[5]	127	1			T54	14		T246	9		T194	14
auto[1]	values[7]	values[6]	121	1			T57	17		T58	8		T241	14
auto[1]	values[7]	values[7]	191	1			T54	65		T71	6		T289	12