Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	822	1			T21	14		T87	21		T33	14
all_values[1]	822	1			T21	14		T87	21		T33	14
all_values[2]	822	1			T21	14		T87	21		T33	14
all_values[3]	822	1			T21	14		T87	21		T33	14
all_values[4]	822	1			T21	14		T87	21		T33	14
all_values[5]	822	1			T21	14		T87	21		T33	14
all_values[6]	822	1			T21	14		T87	21		T33	14
all_values[7]	822	1			T21	14		T87	21		T33	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3511

1

T21

64

T87

88

T33

57

auto[1]

3065

1

T21

48

T87

80

T33

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2636

1

T21

38

T87

69

T33

45

auto[1]

3940

1

T21

74

T87

99

T33

67

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3778

1

T21

52

T87

100

T33

65

auto[1]

2798

1

T21

60

T87

68

T33

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	165	1			T21	3		T87	2		T33	5
all_values[0]	auto[0]	auto[0]	auto[1]	92	1			T21	2		T87	3		T33	1
all_values[0]	auto[0]	auto[1]	auto[0]	141	1			T21	1		T87	3		T33	3
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T21	2		T87	3		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	204	1			T21	6		T87	5		T33	4
all_values[0]	auto[1]	auto[1]	auto[1]	136	1			T87	5		T167	3		T64	5
all_values[1]	auto[0]	auto[0]	auto[0]	161	1			T21	1		T87	4		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T21	2		T87	2		T64	2
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T21	1		T87	2		T33	6
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T21	2		T87	4		T33	2
all_values[1]	auto[1]	auto[0]	auto[1]	174	1			T21	3		T87	9		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	169	1			T21	5		T33	5		T167	6
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T21	3		T87	2		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	67	1			T87	1		T33	1		T167	1
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T21	3		T87	5		T33	2
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T87	5		T33	3		T34	1
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T21	3		T87	5		T33	4
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T21	5		T87	3		T33	3
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T21	2		T87	5		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T21	1		T87	2		T33	2
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T21	3		T87	3		T33	1
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T21	1		T87	3		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	194	1			T21	4		T87	2		T33	5
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T21	3		T87	6		T33	4
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T21	3		T87	6		T33	2
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T21	1		T87	1		T33	3
all_values[4]	auto[0]	auto[1]	auto[0]	131	1			T21	1		T87	5		T34	1
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T87	1		T33	1		T167	2
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T21	6		T87	2		T33	8
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T21	3		T87	6		T34	1
all_values[5]	auto[0]	auto[0]	auto[0]	253	1			T21	3		T87	6		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T21	4		T87	6		T33	9
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T21	3		T87	4		T34	1
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T21	4		T87	5		T33	4
all_values[6]	auto[0]	auto[0]	auto[0]	191	1			T21	3		T87	7		T33	7
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T21	1		T87	3		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	117	1			T21	1		T87	4		T33	1
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T34	1		T167	1		T174	2
all_values[6]	auto[1]	auto[0]	auto[1]	185	1			T21	6		T87	3		T33	5
all_values[6]	auto[1]	auto[1]	auto[1]	160	1			T21	3		T87	4		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	146	1			T21	3		T87	6		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T21	1		T87	2		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T21	3		T87	3		T33	3
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T21	1		T87	1		T33	3
all_values[7]	auto[1]	auto[0]	auto[1]	208	1			T21	4		T87	6		T33	2
all_values[7]	auto[1]	auto[1]	auto[1]	165	1			T21	2		T87	3		T33	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal