Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7543591	1			T1	1		T2	1		T4	1
all_values[1]	7543591	1			T1	1		T2	1		T4	1
all_values[2]	7543591	1			T1	1		T2	1		T4	1
all_values[3]	7543591	1			T1	1		T2	1		T4	1
all_values[4]	7543591	1			T1	1		T2	1		T4	1
all_values[5]	7543591	1			T1	1		T2	1		T4	1
all_values[6]	7543591	1			T1	1		T2	1		T4	1
all_values[7]	7543591	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59349428

1

T1

8

T2

8

T4

8

auto[1]

999300

1

T18

108

T69

99

T71

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60266443

1

T1

8

T2

8

T4

8

auto[1]

82285

1

T10

499

T12

424

T15

343

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7284722	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	46920	1			T10	277		T12	286		T15	208
all_values[0]	auto[1]	auto[0]	210484	1			T18	8		T69	5		T71	5
all_values[0]	auto[1]	auto[1]	1465	1			T18	4		T69	4		T71	8
all_values[1]	auto[0]	auto[0]	7480037	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	22582	1			T10	158		T12	138		T15	135
all_values[1]	auto[1]	auto[0]	39969	1			T18	8		T69	9		T71	9
all_values[1]	auto[1]	auto[1]	1003	1			T18	8		T69	8		T71	4
all_values[2]	auto[0]	auto[0]	7494799	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	7835	1			T10	64		T18	144		T28	30
all_values[2]	auto[1]	auto[0]	40395	1			T18	7		T69	11		T71	11
all_values[2]	auto[1]	auto[1]	562	1			T18	6		T69	3		T71	4
all_values[3]	auto[0]	auto[0]	7332592	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	191	1			T18	3		T69	4		T71	6
all_values[3]	auto[1]	auto[0]	210617	1			T18	13		T69	5		T71	1
all_values[3]	auto[1]	auto[1]	191	1			T18	7		T69	2		T71	2
all_values[4]	auto[0]	auto[0]	7333777	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	165	1			T18	3		T69	5		T71	6
all_values[4]	auto[1]	auto[0]	209482	1			T18	5		T69	8		T71	5
all_values[4]	auto[1]	auto[1]	167	1			T18	6		T69	5		T71	4
all_values[5]	auto[0]	auto[0]	7487578	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	353	1			T18	1		T69	6		T175	7
all_values[5]	auto[1]	auto[0]	55507	1			T18	8		T69	12		T71	2
all_values[5]	auto[1]	auto[1]	153	1			T18	7		T69	2		T71	4
all_values[6]	auto[0]	auto[0]	7346677	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	163	1			T18	1		T69	2		T71	2
all_values[6]	auto[1]	auto[0]	196562	1			T18	4		T69	6		T71	15
all_values[6]	auto[1]	auto[1]	189	1			T18	5		T69	4		T71	3
all_values[7]	auto[0]	auto[0]	7510861	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	176	1			T18	5		T69	4		T71	2
all_values[7]	auto[1]	auto[0]	32384	1			T18	7		T69	12		T71	15
all_values[7]	auto[1]	auto[1]	170	1			T18	5		T69	3		T71	1