Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	42195	1			T1	22		T4	22		T6	8
auto[SpiFlashAddrCfg]	9155	1			T6	6		T7	12		T9	6
auto[SpiFlashAddr3b]	11289	1			T2	6		T5	4		T6	8
auto[SpiFlashAddr4b]	9272	1			T2	12		T6	10		T7	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41458

1

T1

22

T2

18

T4

22

auto[1]

30453

1

T6

32

T10

290

T12

230

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38401

1

T1

22

T2

14

T4

16

auto[1]

33510

1

T2

4

T4

6

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	47872	1			T1	22		T4	22		T5	4
values[1]	1258	1			T7	4		T10	6		T12	7
values[2]	1702	1			T10	18		T12	16		T15	7
values[3]	1767	1			T10	13		T12	11		T30	2
values[4]	1810	1			T10	9		T12	22		T15	2
values[5]	1847	1			T2	16		T10	11		T12	11
values[6]	1780	1			T7	6		T10	13		T12	17
values[7]	1766	1			T10	17		T12	16		T15	5
values[8]	12109	1			T2	2		T6	8		T7	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34748

1

T1

22

T2

18

T4

22

auto[1]

37163

1

T9

6

T10

606

T18

790

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

69346

1

T1

22

T2

18

T4

22

write

2565

1

T6

6

T7

4

T10

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24012

1

T1

22

T2

10

T6

8

valids[0x1]

47899

1

T2

8

T4

22

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1946	1			T4	8		T6	2		T10	23
internal_process_ops[0x5a]	1889	1			T5	2		T10	20		T12	15
internal_process_ops[0x05]	25462	1			T7	2		T10	224		T12	173
internal_process_ops[0x35]	1893	1			T4	8		T10	19		T12	10
internal_process_ops[0x15]	1913	1			T4	6		T6	4		T10	13
internal_process_ops[0x03]	1321	1			T2	4		T5	2		T9	3
internal_process_ops[0x0b]	1352	1			T2	4		T6	10		T10	4
internal_process_ops[0x3b]	1322	1			T2	2		T6	8		T7	4
internal_process_ops[0x6b]	1316	1			T2	8		T10	6		T12	16
internal_process_ops[0xbb]	1268	1			T7	2		T10	6		T12	9
internal_process_ops[0xeb]	1313	1			T9	3		T10	2		T12	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70650

1

T1

22

T2

18

T4

22

auto[1]

1261

1

T6

6

T10

11

T12

15

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69336

1

T1

22

T2

18

T4

22

auto[1]

2575

1

T10

23

T12

16

T15

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11496

1

T1

22

T4

22

T7

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6896

1

T6

8

T12

106

T15

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2577

1

T7

12

T12

29

T32

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2099

1

T12

34

T15

11

T33

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3234

1

T2

6

T5

4

T7

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2541

1

T6

8

T12

47

T15

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2555

1

T2

12

T7

4

T12

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2165

1

T6

10

T12

29

T15

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

75

1

T33

3

T39

3

T161

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

71

1

T12

3

T34

2

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

64

1

T12

3

T33

2

T161

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T12

2

T34

2

T60

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T12

5

T15

3

T167

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T12

2

T37

1

T39

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T12

1

T33

4

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

78

1

T6

6

T12

4

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

77

1

T39

1

T40

1

T168

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T12

2

T33

1

T39

8

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

56

1

T12

2

T37

1

T39

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

76

1

T12

1

T34

4

T40

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

104

1

T7

4

T98

4

T33

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

71

1

T34

1

T39

3

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T15

1

T33

2

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T12

1

T33

1

T34

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13679

1

T10

199

T18

406

T27

32

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9517

1

T10

181

T18

144

T27

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1909

1

T9

6

T10

23

T18

34

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1913

1

T10

32

T18

26

T27

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2595

1

T10

50

T18

41

T27

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2257

1

T10

30

T18

48

T27

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2080

1

T10

31

T18

28

T27

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1833

1

T10

36

T18

39

T27

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

81

1

T18

2

T88

2

T169

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T10

1

T18

2

T88

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

76

1

T18

3

T28

3

T64

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T18

3

T170

2

T171

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

78

1

T10

1

T18

1

T28

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T10

3

T18

2

T161

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T10

1

T65

1

T171

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T10

1

T18

3

T172

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

75

1

T10

2

T18

1

T88

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T10

4

T18

1

T39

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

113

1

T10

5

T65

2

T170

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T10

1

T65

1

T171

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T10

2

T18

2

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

81

1

T64

2

T65

2

T39

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

74

1

T10

2

T18

3

T170

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

65

1

T10

1

T18

1

T28

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4768	1			T1	22		T7	6		T8	8
auto[0]	values[0]	valids[0x1]	16815	1			T4	22		T5	4		T6	24
auto[0]	values[1]	valids[0x1]	625	1			T7	4		T12	7		T15	1
auto[0]	values[2]	valids[0x0]	622	1			T12	9		T15	5		T173	2
auto[0]	values[2]	valids[0x1]	353	1			T12	7		T15	2		T98	2
auto[0]	values[3]	valids[0x0]	597	1			T12	9		T30	2		T15	5
auto[0]	values[3]	valids[0x1]	355	1			T12	2		T167	4		T33	2
auto[0]	values[4]	valids[0x0]	620	1			T12	12		T15	1		T121	2
auto[0]	values[4]	valids[0x1]	407	1			T12	10		T15	1		T167	2
auto[0]	values[5]	valids[0x0]	609	1			T2	8		T12	7		T32	4
auto[0]	values[5]	valids[0x1]	393	1			T2	8		T12	4		T15	3
auto[0]	values[6]	valids[0x0]	613	1			T7	4		T12	11		T15	1
auto[0]	values[6]	valids[0x1]	341	1			T7	2		T12	6		T174	4
auto[0]	values[7]	valids[0x0]	655	1			T12	10		T15	3		T36	2
auto[0]	values[7]	valids[0x1]	322	1			T12	6		T15	2		T36	2
auto[0]	values[8]	valids[0x0]	4167	1			T2	2		T6	8		T7	8
auto[0]	values[8]	valids[0x1]	2486	1			T12	43		T30	2		T32	2
auto[1]	values[0]	valids[0x0]	5224	1			T10	87		T18	92		T27	25
auto[1]	values[0]	valids[0x1]	21065	1			T9	3		T10	351		T18	498
auto[1]	values[1]	valids[0x1]	633	1			T10	6		T18	20		T27	2
auto[1]	values[2]	valids[0x0]	430	1			T10	9		T18	1		T27	1
auto[1]	values[2]	valids[0x1]	297	1			T10	9		T18	7		T27	1
auto[1]	values[3]	valids[0x0]	501	1			T10	9		T18	6		T27	1
auto[1]	values[3]	valids[0x1]	314	1			T10	4		T18	6		T27	1
auto[1]	values[4]	valids[0x0]	477	1			T10	5		T18	8		T46	1
auto[1]	values[4]	valids[0x1]	306	1			T10	4		T18	5		T27	4
auto[1]	values[5]	valids[0x0]	489	1			T10	7		T18	7		T27	3
auto[1]	values[5]	valids[0x1]	356	1			T10	4		T18	6		T28	1
auto[1]	values[6]	valids[0x0]	494	1			T10	7		T18	5		T27	1
auto[1]	values[6]	valids[0x1]	332	1			T10	6		T18	6		T27	1
auto[1]	values[7]	valids[0x0]	508	1			T10	12		T18	15		T27	1
auto[1]	values[7]	valids[0x1]	281	1			T10	5		T18	3		T27	2
auto[1]	values[8]	valids[0x0]	3238	1			T9	3		T10	44		T18	67
auto[1]	values[8]	valids[0x1]	2218	1			T10	37		T18	38		T27	4