Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19382

1

T1

12

T2

8

T4

28

auto[1]

25929

1

T10

222

T12

178

T15

44

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16415

1

T1

12

T2

8

T4

14

auto[1]

28896

1

T4

14

T10

256

T12

196

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7664	1			T1	2		T2	2		T4	11
auto[524288:1048575]	5287	1			T1	3		T2	4		T9	1
auto[1048576:1572863]	6246	1			T1	1		T4	1		T5	1
auto[1572864:2097151]	5099	1			T4	1		T9	3		T10	142
auto[2097152:2621439]	5081	1			T1	3		T4	11		T9	1
auto[2621440:3145727]	4807	1			T1	1		T5	1		T9	1
auto[3145728:3670015]	5593	1			T2	1		T4	1		T10	17
auto[3670016:4194303]	5534	1			T1	2		T2	1		T4	3

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44367

1

T1

12

T2

8

T4

28

auto[1]

944

1

T10

26

T12

1

T18

14

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36685

1

T1

8

T2

8

T4

28

auto[1]

8626

1

T1

4

T10

29

T12

26

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1968	1			T1	2		T2	2		T4	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	779	1			T4	6		T10	5		T12	7
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1358	1			T1	1		T2	4		T9	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	552	1			T10	3		T12	2		T18	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1503	1			T1	1		T4	1		T5	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	549	1			T10	2		T12	7		T15	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1277	1			T4	1		T9	3		T10	25
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	490	1			T10	14		T12	1		T18	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1277	1			T1	2		T4	5		T9	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	528	1			T4	6		T10	8		T12	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1192	1			T5	1		T9	1		T10	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	454	1			T10	7		T12	4		T15	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1348	1			T2	1		T10	10		T12	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	494	1			T4	1		T10	7		T12	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1383	1			T1	2		T2	1		T4	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	536	1			T4	1		T10	6		T12	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	330	1			T10	4		T18	3		T46	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	146	1			T10	1		T18	1		T34	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	323	1			T1	2		T12	1		T27	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	157	1			T12	1		T27	2		T33	8
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	320	1			T10	1		T12	2		T15	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	146	1			T12	2		T18	1		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	281	1			T10	3		T12	2		T18	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	138	1			T10	2		T15	1		T18	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	285	1			T1	1		T10	1		T12	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	138	1			T18	1		T33	1		T34	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	290	1			T1	1		T10	4		T45	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	147	1			T10	2		T18	1		T27	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	302	1			T12	4		T18	5		T27	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	140	1			T12	1		T18	3		T27	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	395	1			T10	7		T12	2		T18	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	156	1			T18	1		T27	1		T33	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	356	1			T10	3		T33	1		T46	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3363	1			T10	15		T33	1		T46	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	255	1			T10	2		T12	3		T18	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2084	1			T10	17		T12	5		T18	32
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	295	1			T10	3		T12	1		T15	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2647	1			T10	12		T12	4		T15	22
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	227	1			T10	8		T12	2		T33	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2189	1			T10	90		T12	54		T33	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	242	1			T10	2		T12	1		T18	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2079	1			T10	18		T12	1		T18	44
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	224	1			T10	2		T12	3		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1887	1			T10	15		T12	8		T15	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	246	1			T12	2		T18	2		T34	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2495	1			T12	81		T18	23		T34	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	242	1			T10	2		T12	1		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2166	1			T10	29		T12	2		T15	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	67	1			T46	1		T34	1		T65	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	655	1			T46	44		T34	2		T65	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	73	1			T33	3		T170	2		T40	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	485	1			T33	8		T170	10		T40	26
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	66	1			T12	1		T33	6		T65	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	720	1			T12	2		T33	13		T65	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	40	1			T18	2		T33	1		T42	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	457	1			T18	22		T33	1		T42	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	58	1			T34	1		T65	1		T170	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	474	1			T34	1		T65	2		T170	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	58	1			T18	1		T65	1		T195	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	555	1			T18	16		T65	1		T195	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	53	1			T12	1		T18	3		T65	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	515	1			T12	2		T18	80		T65	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	81	1			T10	1		T12	1		T28	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	575	1			T10	3		T12	3		T28	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15271	1			T1	8		T2	8		T4	28
auto[0]	auto[0]	auto[1]	417	1			T10	13		T18	10		T64	1
auto[0]	auto[1]	auto[0]	3595	1			T1	4		T10	24		T12	16
auto[0]	auto[1]	auto[1]	99	1			T10	1		T18	3		T88	2
auto[1]	auto[0]	auto[0]	20658	1			T10	207		T12	167		T15	44
auto[1]	auto[0]	auto[1]	339	1			T10	11		T12	1		T28	1
auto[1]	auto[1]	auto[0]	4843	1			T10	3		T12	10		T18	123
auto[1]	auto[1]	auto[1]	89	1			T10	1		T18	1		T33	1