Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20500

1

T1

22

T2

18

T4

22

auto[1]

14248

1

T6

32

T12

230

T15

49

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4093	1			T4	22		T108	24		T212	6
values[1]	4115	1			T12	142		T45	8		T33	65
values[2]	4058	1			T1	22		T12	20		T36	24
values[3]	4482	1			T6	32		T12	20		T31	4
values[4]	3923	1			T8	8		T12	85		T35	28
values[5]	4798	1			T5	4		T7	30		T12	94
values[6]	4473	1			T12	139		T15	23		T173	14
values[7]	4806	1			T2	18		T12	22		T15	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4836	1			T12	119		T36	24		T121	10
values[1]	4026	1			T1	22		T30	10		T31	4
values[2]	4722	1			T7	30		T8	8		T12	44
values[3]	4015	1			T6	32		T12	86		T167	24
values[4]	4299	1			T4	22		T12	64		T15	53
values[5]	4297	1			T5	4		T12	62		T35	28
values[6]	4147	1			T45	8		T98	16		T33	97
values[7]	4406	1			T2	18		T12	147		T15	32

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	163	1			T213	8		T214	7		T188	9
auto[0]	values[0]	values[1]	269	1			T212	6		T39	42		T195	16
auto[0]	values[0]	values[2]	295	1			T41	11		T47	15		T134	11
auto[0]	values[0]	values[3]	192	1			T215	16		T216	8		T217	30
auto[0]	values[0]	values[4]	342	1			T4	22		T108	24		T39	13
auto[0]	values[0]	values[5]	324	1			T47	14		T60	12		T48	14
auto[0]	values[0]	values[6]	418	1			T39	11		T40	43		T47	27
auto[0]	values[0]	values[7]	343	1			T218	12		T47	12		T60	12
auto[0]	values[1]	values[0]	366	1			T12	5		T34	9		T40	42
auto[0]	values[1]	values[1]	266	1			T40	8		T86	13		T60	13
auto[0]	values[1]	values[2]	225	1			T219	12		T39	6		T42	13
auto[0]	values[1]	values[3]	135	1			T34	17		T39	9		T220	4
auto[0]	values[1]	values[4]	350	1			T33	13		T195	14		T60	9
auto[0]	values[1]	values[5]	232	1			T12	14		T39	14		T221	10
auto[0]	values[1]	values[6]	298	1			T45	8		T33	20		T86	11
auto[0]	values[1]	values[7]	317	1			T12	91		T41	22		T135	23
auto[0]	values[2]	values[0]	328	1			T36	24		T34	18		T39	43
auto[0]	values[2]	values[1]	337	1			T1	22		T39	12		T48	13
auto[0]	values[2]	values[2]	487	1			T37	14		T40	63		T218	15
auto[0]	values[2]	values[3]	225	1			T39	11		T222	2		T223	2
auto[0]	values[2]	values[4]	423	1			T12	13		T33	14		T174	16
auto[0]	values[2]	values[5]	234	1			T33	11		T60	17		T188	7
auto[0]	values[2]	values[6]	191	1			T34	9		T37	18		T41	10
auto[0]	values[2]	values[7]	227	1			T40	25		T47	12		T60	11
auto[0]	values[3]	values[0]	369	1			T33	25		T39	28		T195	6
auto[0]	values[3]	values[1]	390	1			T31	4		T41	11		T42	16
auto[0]	values[3]	values[2]	392	1			T32	8		T34	13		T191	32
auto[0]	values[3]	values[3]	270	1			T12	11		T167	24		T33	10
auto[0]	values[3]	values[4]	288	1			T15	27		T34	12		T224	14
auto[0]	values[3]	values[5]	412	1			T34	10		T225	6		T195	13
auto[0]	values[3]	values[6]	255	1			T33	16		T47	19		T60	9
auto[0]	values[3]	values[7]	363	1			T15	26		T39	13		T40	17
auto[0]	values[4]	values[0]	371	1			T33	16		T226	8		T134	16
auto[0]	values[4]	values[1]	381	1			T33	14		T161	12		T40	13
auto[0]	values[4]	values[2]	346	1			T8	8		T12	12		T33	12
auto[0]	values[4]	values[3]	293	1			T227	6		T228	14		T189	8
auto[0]	values[4]	values[4]	289	1			T12	11		T39	9		T195	29
auto[0]	values[4]	values[5]	226	1			T12	28		T35	28		T34	7
auto[0]	values[4]	values[6]	204	1			T98	16		T33	12		T41	18
auto[0]	values[4]	values[7]	308	1			T39	23		T47	25		T134	10
auto[0]	values[5]	values[0]	365	1			T12	8		T121	10		T33	7
auto[0]	values[5]	values[1]	255	1			T30	10		T15	12		T135	31
auto[0]	values[5]	values[2]	338	1			T7	30		T34	13		T40	12
auto[0]	values[5]	values[3]	677	1			T12	23		T33	15		T40	9
auto[0]	values[5]	values[4]	279	1			T47	16		T48	12		T193	42
auto[0]	values[5]	values[5]	393	1			T5	4		T34	11		T39	13
auto[0]	values[5]	values[6]	229	1			T40	27		T185	22		T135	27
auto[0]	values[5]	values[7]	411	1			T12	14		T39	68		T40	12
auto[0]	values[6]	values[0]	522	1			T12	16		T39	12		T41	16
auto[0]	values[6]	values[1]	242	1			T15	18		T39	14		T47	55
auto[0]	values[6]	values[2]	322	1			T12	17		T39	15		T41	15
auto[0]	values[6]	values[3]	289	1			T12	10		T34	5		T39	5
auto[0]	values[6]	values[4]	199	1			T39	17		T86	9		T48	14
auto[0]	values[6]	values[5]	416	1			T173	14		T34	13		T81	30
auto[0]	values[6]	values[6]	358	1			T229	2		T40	11		T41	12
auto[0]	values[6]	values[7]	295	1			T12	6		T33	16		T207	22
auto[0]	values[7]	values[0]	436	1			T40	12		T41	25		T42	11
auto[0]	values[7]	values[1]	327	1			T230	26		T196	14		T231	16
auto[0]	values[7]	values[2]	205	1			T33	9		T195	11		T218	11
auto[0]	values[7]	values[3]	371	1			T34	12		T161	26		T232	115
auto[0]	values[7]	values[4]	422	1			T12	13		T15	5		T34	22
auto[0]	values[7]	values[5]	290	1			T39	63		T161	10		T183	14
auto[0]	values[7]	values[6]	384	1			T41	6		T47	10		T60	16
auto[0]	values[7]	values[7]	331	1			T2	18		T34	25		T39	42
auto[1]	values[0]	values[0]	243	1			T214	13		T188	75		T233	7
auto[1]	values[0]	values[1]	163	1			T39	8		T195	6		T48	21
auto[1]	values[0]	values[2]	200	1			T41	9		T47	7		T134	24
auto[1]	values[0]	values[3]	122	1			T188	17		T21	11		T201	12
auto[1]	values[0]	values[4]	236	1			T39	33		T47	35		T134	5
auto[1]	values[0]	values[5]	211	1			T47	6		T60	8		T48	9
auto[1]	values[0]	values[6]	365	1			T39	9		T40	5		T47	16
auto[1]	values[0]	values[7]	207	1			T218	8		T234	4		T47	10
auto[1]	values[1]	values[0]	265	1			T12	16		T34	23		T40	8
auto[1]	values[1]	values[1]	262	1			T40	12		T235	22		T86	9
auto[1]	values[1]	values[2]	319	1			T39	14		T42	68		T218	12
auto[1]	values[1]	values[3]	234	1			T34	3		T39	47		T236	3
auto[1]	values[1]	values[4]	224	1			T33	7		T237	14		T195	6
auto[1]	values[1]	values[5]	205	1			T12	6		T39	8		T134	12
auto[1]	values[1]	values[6]	204	1			T33	25		T86	9		T193	3
auto[1]	values[1]	values[7]	213	1			T12	10		T41	20		T135	7
auto[1]	values[2]	values[0]	183	1			T34	11		T39	8		T47	9
auto[1]	values[2]	values[1]	231	1			T39	50		T48	11		T186	6
auto[1]	values[2]	values[2]	213	1			T37	6		T40	7		T218	5
auto[1]	values[2]	values[3]	144	1			T39	9		T47	7		T238	9
auto[1]	values[2]	values[4]	229	1			T12	7		T33	8		T39	4
auto[1]	values[2]	values[5]	170	1			T33	9		T60	5		T188	13
auto[1]	values[2]	values[6]	204	1			T34	13		T37	9		T41	10
auto[1]	values[2]	values[7]	232	1			T40	15		T47	8		T60	9
auto[1]	values[3]	values[0]	211	1			T33	3		T39	17		T195	29
auto[1]	values[3]	values[1]	234	1			T41	9		T42	5		T186	8
auto[1]	values[3]	values[2]	244	1			T34	7		T39	11		T195	12
auto[1]	values[3]	values[3]	247	1			T6	32		T12	9		T33	10
auto[1]	values[3]	values[4]	163	1			T15	6		T34	8		T39	10
auto[1]	values[3]	values[5]	181	1			T34	15		T195	10		T60	6
auto[1]	values[3]	values[6]	216	1			T33	7		T47	2		T60	12
auto[1]	values[3]	values[7]	247	1			T15	6		T39	8		T40	3
auto[1]	values[4]	values[0]	262	1			T33	6		T134	13		T135	10
auto[1]	values[4]	values[1]	112	1			T33	6		T161	8		T40	7
auto[1]	values[4]	values[2]	268	1			T12	9		T33	16		T40	11
auto[1]	values[4]	values[3]	156	1			T189	17		T239	6		T196	12
auto[1]	values[4]	values[4]	174	1			T12	11		T39	11		T195	20
auto[1]	values[4]	values[5]	230	1			T12	14		T34	14		T37	16
auto[1]	values[4]	values[6]	156	1			T33	17		T41	5		T47	7
auto[1]	values[4]	values[7]	147	1			T39	17		T47	20		T134	10
auto[1]	values[5]	values[0]	383	1			T12	14		T33	13		T34	9
auto[1]	values[5]	values[1]	127	1			T15	17		T38	20		T135	7
auto[1]	values[5]	values[2]	172	1			T34	9		T40	8		T184	4
auto[1]	values[5]	values[3]	260	1			T12	23		T33	5		T40	15
auto[1]	values[5]	values[4]	232	1			T47	4		T48	8		T193	6
auto[1]	values[5]	values[5]	282	1			T34	9		T39	8		T60	3
auto[1]	values[5]	values[6]	115	1			T40	9		T185	5		T135	9
auto[1]	values[5]	values[7]	280	1			T12	12		T39	28		T40	13
auto[1]	values[6]	values[0]	167	1			T12	60		T39	9		T41	8
auto[1]	values[6]	values[1]	242	1			T15	5		T39	6		T47	13
auto[1]	values[6]	values[2]	276	1			T12	6		T39	5		T41	5
auto[1]	values[6]	values[3]	265	1			T12	10		T34	15		T39	15
auto[1]	values[6]	values[4]	129	1			T39	3		T86	11		T48	6
auto[1]	values[6]	values[5]	237	1			T34	8		T47	7		T240	7
auto[1]	values[6]	values[6]	280	1			T40	44		T41	8		T86	21
auto[1]	values[6]	values[7]	234	1			T12	14		T33	4		T39	5
auto[1]	values[7]	values[0]	202	1			T40	17		T41	23		T42	26
auto[1]	values[7]	values[1]	188	1			T241	24		T196	6		T231	4
auto[1]	values[7]	values[2]	420	1			T33	12		T195	17		T218	15
auto[1]	values[7]	values[3]	135	1			T34	8		T161	10		T242	10
auto[1]	values[7]	values[4]	320	1			T12	9		T15	15		T34	10
auto[1]	values[7]	values[5]	254	1			T39	7		T161	11		T86	24
auto[1]	values[7]	values[6]	270	1			T41	14		T47	10		T60	6
auto[1]	values[7]	values[7]	251	1			T34	15		T39	9		T41	10