Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T12	4		T30	4		T31	4
auto[ReadAddrCrossIntoMailbox]	319	1			T2	6		T12	5		T33	2
auto[ReadAddrCrossOutOfMailbox]	350	1			T12	5		T33	3		T34	3
auto[ReadAddrCrossAllMailbox]	223	1			T2	6		T12	4		T32	2
auto[ReadAddrOutsideMailbox]	4261	1			T2	6		T5	2		T6	18

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2824

1

T2

9

T5

1

T6

9

auto[1]

2748

1

T2

9

T5

1

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	951	1			T2	4		T5	2		T12	11
read_ops[0x0b]	974	1			T2	4		T6	10		T12	26
read_ops[0x3b]	925	1			T2	2		T6	8		T7	4
read_ops[0x6b]	905	1			T2	8		T12	16		T30	2
read_ops[0xbb]	905	1			T7	2		T12	9		T31	2
read_ops[0xeb]	912	1			T12	9		T32	4		T15	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T30	1		T173	4		T39	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T30	1		T173	4		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T39	2		T60	1		T243	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T12	1		T40	1		T60	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T39	2		T40	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T161	1		T218	1		T184	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T47	1		T60	1		T186	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T34	1		T86	1		T60	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T2	2		T5	1		T12	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	391	1			T2	2		T5	1		T12	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T33	1		T244	1		T39	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T12	1		T33	2		T244	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T2	1		T40	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T2	1		T12	1		T39	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T12	1		T39	2		T40	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T12	3		T34	1		T60	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T2	1		T12	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T2	1		T32	1		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	386	1			T6	5		T12	11		T15	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	366	1			T6	5		T12	8		T173	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T12	1		T31	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T31	1		T32	1		T39	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T39	1		T161	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T12	1		T161	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	40	1			T34	1		T161	1		T86	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T12	1		T33	1		T39	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T2	1		T40	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T2	1		T33	1		T39	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T6	4		T7	2		T12	9
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T6	4		T7	2		T12	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T12	2		T30	1		T34	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T30	1		T218	1		T227	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T2	2		T12	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T2	2		T12	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T40	1		T86	2		T135	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T33	1		T34	1		T60	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T2	1		T12	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T2	1		T39	1		T41	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	368	1			T2	1		T12	5		T35	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T2	1		T12	6		T15	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T31	1		T33	1		T244	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T31	1		T244	1		T39	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T33	2		T185	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T39	2		T42	1		T86	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T86	1		T47	2		T60	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T33	1		T161	1		T40	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T12	1		T15	1		T60	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T39	1		T40	2		T86	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	350	1			T7	1		T12	5		T15	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T7	1		T12	3		T15	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T161	1		T86	1		T47	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T34	1		T39	2		T218	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T39	1		T60	1		T245	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T39	1		T40	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T39	2		T47	4		T48	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T39	2		T86	1		T60	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T39	1		T60	1		T238	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T12	1		T86	1		T60	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	340	1			T12	5		T32	2		T173	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	362	1			T12	3		T32	2		T15	3