Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7543591	1			T1	1		T2	1		T4	1
all_pins[1]	7543591	1			T1	1		T2	1		T4	1
all_pins[2]	7543591	1			T1	1		T2	1		T4	1
all_pins[3]	7543591	1			T1	1		T2	1		T4	1
all_pins[4]	7543591	1			T1	1		T2	1		T4	1
all_pins[5]	7543591	1			T1	1		T2	1		T4	1
all_pins[6]	7543591	1			T1	1		T2	1		T4	1
all_pins[7]	7543591	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	60143290	1			T1	8		T2	8		T4	8
values[0x1]	205438	1			T18	48		T69	31		T71	30
transitions[0x0=>0x1]	204173	1			T18	41		T69	28		T71	22
transitions[0x1=>0x0]	204187	1			T18	41		T69	28		T71	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7542074	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	1517	1			T18	4		T69	4		T71	8
all_pins[0]	transitions[0x0=>0x1]	1163	1			T18	4		T69	3		T71	5
all_pins[0]	transitions[0x1=>0x0]	688	1			T18	8		T69	7		T71	1
all_pins[1]	values[0x0]	7542549	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	1042	1			T18	8		T69	8		T71	4
all_pins[1]	transitions[0x0=>0x1]	604	1			T18	6		T69	8		T71	3
all_pins[1]	transitions[0x1=>0x0]	140	1			T18	4		T69	3		T71	3
all_pins[2]	values[0x0]	7543013	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	578	1			T18	6		T69	3		T71	4
all_pins[2]	transitions[0x0=>0x1]	533	1			T18	4		T69	3		T71	4
all_pins[2]	transitions[0x1=>0x0]	146	1			T18	5		T69	2		T71	2
all_pins[3]	values[0x0]	7543400	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	191	1			T18	7		T69	2		T71	2
all_pins[3]	transitions[0x0=>0x1]	154	1			T18	6		T69	2		T71	1
all_pins[3]	transitions[0x1=>0x0]	130	1			T18	5		T69	5		T71	3
all_pins[4]	values[0x0]	7543424	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	167	1			T18	6		T69	5		T71	4
all_pins[4]	transitions[0x0=>0x1]	136	1			T18	5		T69	3		T71	3
all_pins[4]	transitions[0x1=>0x0]	5638	1			T18	6		T71	3		T161	1112
all_pins[5]	values[0x0]	7537922	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	5669	1			T18	7		T69	2		T71	4
all_pins[5]	transitions[0x0=>0x1]	5396	1			T18	6		T69	2		T71	3
all_pins[5]	transitions[0x1=>0x0]	195831	1			T18	4		T69	4		T71	2
all_pins[6]	values[0x0]	7347487	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	196104	1			T18	5		T69	4		T71	3
all_pins[6]	transitions[0x0=>0x1]	196061	1			T18	5		T69	4		T71	3
all_pins[6]	transitions[0x1=>0x0]	127	1			T18	5		T69	3		T71	1
all_pins[7]	values[0x0]	7543421	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	170	1			T18	5		T69	3		T71	1
all_pins[7]	transitions[0x0=>0x1]	126	1			T18	5		T69	3		T166	2
all_pins[7]	transitions[0x1=>0x0]	1487	1			T18	4		T69	4		T71	7