Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3783	1			T12	163		T98	16		T121	10
values[1]	4184	1			T12	45		T30	10		T32	8
values[2]	4338	1			T1	22		T15	65		T167	24
values[3]	4543	1			T2	18		T12	63		T34	52
values[4]	4519	1			T5	4		T6	32		T7	30
values[5]	4488	1			T8	8		T12	20		T36	24
values[6]	4769	1			T12	98		T15	29		T173	14
values[7]	4124	1			T4	22		T12	46		T31	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4704	1			T6	32		T12	121		T15	32
values[1]	4460	1			T12	24		T15	23		T33	103
values[2]	4057	1			T2	18		T8	8		T12	64
values[3]	5012	1			T12	97		T33	22		T34	91
values[4]	4302	1			T12	40		T31	4		T33	22
values[5]	3970	1			T4	22		T5	4		T12	44
values[6]	4063	1			T12	46		T32	8		T33	20
values[7]	4180	1			T1	22		T7	30		T12	86

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34196

1

T1

22

T2

18

T4

22

auto[1]

552

1

T6

6

T12

15

T33

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	416	1			T12	121		T98	16		T121	10
auto[0]	values[0]	values[1]	430	1			T246	10		T47	79		T60	20
auto[0]	values[0]	values[2]	511	1			T12	22		T40	36		T41	21
auto[0]	values[0]	values[3]	593	1			T39	20		T40	20		T86	40
auto[0]	values[0]	values[4]	488	1			T12	20		T42	21		T47	31
auto[0]	values[0]	values[5]	425	1			T33	28		T34	41		T212	6
auto[0]	values[0]	values[6]	449	1			T195	20		T86	21		T47	51
auto[0]	values[0]	values[7]	401	1			T39	19		T161	54		T40	20
auto[0]	values[1]	values[0]	461	1			T220	4		T235	22		T186	91
auto[0]	values[1]	values[1]	546	1			T33	42		T34	20		T39	24
auto[0]	values[1]	values[2]	426	1			T30	10		T45	8		T195	21
auto[0]	values[1]	values[3]	738	1			T42	20		T86	23		T227	6
auto[0]	values[1]	values[4]	380	1			T39	53		T47	48		T60	20
auto[0]	values[1]	values[5]	493	1			T12	23		T33	20		T229	2
auto[0]	values[1]	values[6]	508	1			T32	8		T86	22		T47	25
auto[0]	values[1]	values[7]	578	1			T12	22		T108	24		T39	95
auto[0]	values[2]	values[0]	639	1			T15	32		T37	27		T39	21
auto[0]	values[2]	values[1]	631	1			T37	20		T39	30		T223	2
auto[0]	values[2]	values[2]	411	1			T167	24		T33	20		T219	12
auto[0]	values[2]	values[3]	535	1			T34	19		T168	18		T60	20
auto[0]	values[2]	values[4]	389	1			T86	31		T186	20		T135	20
auto[0]	values[2]	values[5]	596	1			T15	33		T60	18		T184	20
auto[0]	values[2]	values[6]	398	1			T34	40		T39	50		T218	20
auto[0]	values[2]	values[7]	677	1			T1	22		T34	22		T185	19
auto[0]	values[3]	values[0]	459	1			T39	20		T40	20		T60	20
auto[0]	values[3]	values[1]	614	1			T34	31		T39	21		T41	20
auto[0]	values[3]	values[2]	499	1			T2	18		T12	41		T42	81
auto[0]	values[3]	values[3]	709	1			T12	20		T34	20		T41	21
auto[0]	values[3]	values[4]	647	1			T39	60		T40	25		T41	22
auto[0]	values[3]	values[5]	689	1			T41	23		T237	12		T86	36
auto[0]	values[3]	values[6]	535	1			T207	22		T40	20		T86	21
auto[0]	values[3]	values[7]	333	1			T218	26		T47	43		T193	20
auto[0]	values[4]	values[0]	827	1			T6	26		T39	43		T161	20
auto[0]	values[4]	values[1]	552	1			T12	21		T33	20		T39	21
auto[0]	values[4]	values[2]	591	1			T33	28		T174	16		T34	29
auto[0]	values[4]	values[3]	594	1			T40	45		T60	20		T193	60
auto[0]	values[4]	values[4]	583	1			T40	68		T247	2		T193	33
auto[0]	values[4]	values[5]	462	1			T5	4		T12	21		T35	28
auto[0]	values[4]	values[6]	472	1			T38	18		T39	20		T41	20
auto[0]	values[4]	values[7]	347	1			T7	30		T12	40		T33	23
auto[0]	values[5]	values[0]	604	1			T33	28		T34	20		T40	54
auto[0]	values[5]	values[1]	577	1			T33	21		T37	21		T47	20
auto[0]	values[5]	values[2]	487	1			T8	8		T218	21		T186	44
auto[0]	values[5]	values[3]	848	1			T33	21		T39	39		T40	48
auto[0]	values[5]	values[4]	523	1			T12	16		T34	20		T39	40
auto[0]	values[5]	values[5]	448	1			T191	32		T183	14		T194	10
auto[0]	values[5]	values[6]	448	1			T39	20		T41	40		T248	21
auto[0]	values[5]	values[7]	486	1			T36	24		T33	23		T34	20
auto[0]	values[6]	values[0]	524	1			T173	14		T34	20		T41	20
auto[0]	values[6]	values[1]	711	1			T33	20		T40	96		T195	29
auto[0]	values[6]	values[2]	613	1			T34	20		T40	39		T41	27
auto[0]	values[6]	values[3]	594	1			T12	74		T34	27		T39	90
auto[0]	values[6]	values[4]	733	1			T33	22		T195	20		T47	20
auto[0]	values[6]	values[5]	282	1			T41	18		T60	18		T186	80
auto[0]	values[6]	values[6]	592	1			T33	20		T249	12		T134	89
auto[0]	values[6]	values[7]	632	1			T12	22		T15	29		T225	6
auto[0]	values[7]	values[0]	705	1			T33	20		T42	35		T218	18
auto[0]	values[7]	values[1]	324	1			T15	23		T86	20		T60	20
auto[0]	values[7]	values[2]	453	1			T161	21		T250	8		T134	33
auto[0]	values[7]	values[3]	325	1			T34	21		T195	20		T218	25
auto[0]	values[7]	values[4]	473	1			T31	4		T39	20		T40	24
auto[0]	values[7]	values[5]	512	1			T4	22		T15	20		T39	20
auto[0]	values[7]	values[6]	602	1			T12	44		T251	24		T135	85
auto[0]	values[7]	values[7]	668	1			T40	40		T41	20		T81	30
auto[1]	values[0]	values[0]	2	1			T47	2		-	-		-	-
auto[1]	values[0]	values[1]	7	1			T48	1		T134	1		T252	1
auto[1]	values[0]	values[2]	6	1			T134	2		T253	1		T254	2
auto[1]	values[0]	values[3]	13	1			T60	1		T245	7		T255	1
auto[1]	values[0]	values[4]	17	1			T47	3		T243	1		T256	5
auto[1]	values[0]	values[5]	9	1			T34	4		T39	2		T188	1
auto[1]	values[0]	values[6]	5	1			T86	1		T253	1		T257	2
auto[1]	values[0]	values[7]	11	1			T39	1		T161	2		T86	1
auto[1]	values[1]	values[0]	5	1			T135	1		T188	1		T258	1
auto[1]	values[1]	values[1]	7	1			T34	1		T39	1		T156	2
auto[1]	values[1]	values[2]	6	1			T60	2		T134	1		T193	2
auto[1]	values[1]	values[3]	9	1			T86	1		T185	1		T135	2
auto[1]	values[1]	values[4]	7	1			T39	3		T239	2		T259	1
auto[1]	values[1]	values[5]	3	1			T188	1		T239	1		T260	1
auto[1]	values[1]	values[6]	7	1			T47	2		T185	1		T193	1
auto[1]	values[1]	values[7]	10	1			T184	2		T240	1		T261	1
auto[1]	values[2]	values[0]	15	1			T47	3		T233	3		T262	2
auto[1]	values[2]	values[1]	5	1			T236	2		T263	2		T264	1
auto[1]	values[2]	values[2]	8	1			T47	1		T196	5		T265	1
auto[1]	values[2]	values[3]	6	1			T34	1		T134	1		T266	1
auto[1]	values[2]	values[4]	4	1			T86	3		T267	1		-	-
auto[1]	values[2]	values[5]	9	1			T60	2		T214	1		T266	1
auto[1]	values[2]	values[6]	8	1			T39	1		T184	2		T245	1
auto[1]	values[2]	values[7]	7	1			T185	1		T134	2		T188	1
auto[1]	values[3]	values[0]	5	1			T188	2		T206	2		T267	1
auto[1]	values[3]	values[1]	13	1			T34	1		T47	1		T189	2
auto[1]	values[3]	values[2]	5	1			T12	1		T195	1		T239	2
auto[1]	values[3]	values[3]	5	1			T12	1		T47	1		T197	2
auto[1]	values[3]	values[4]	9	1			T39	2		T47	3		T184	1
auto[1]	values[3]	values[5]	12	1			T237	2		T47	1		T21	4
auto[1]	values[3]	values[6]	6	1			T86	1		T185	1		T201	1
auto[1]	values[3]	values[7]	3	1			T255	1		T268	2		-	-
auto[1]	values[4]	values[0]	14	1			T6	6		T39	3		T135	2
auto[1]	values[4]	values[1]	13	1			T12	3		T195	2		T60	1
auto[1]	values[4]	values[2]	16	1			T33	1		T34	3		T39	1
auto[1]	values[4]	values[3]	10	1			T40	3		T193	1		T206	2
auto[1]	values[4]	values[4]	11	1			T40	2		T245	2		T188	2
auto[1]	values[4]	values[5]	7	1			T86	1		T47	2		T135	1
auto[1]	values[4]	values[6]	15	1			T38	2		T188	1		T269	2
auto[1]	values[4]	values[7]	5	1			T12	2		T243	2		T270	1
auto[1]	values[5]	values[0]	6	1			T40	1		T184	1		T258	2
auto[1]	values[5]	values[1]	7	1			T37	2		T201	2		T253	1
auto[1]	values[5]	values[2]	8	1			T242	2		T271	1		T94	3
auto[1]	values[5]	values[3]	13	1			T33	1		T39	1		T40	2
auto[1]	values[5]	values[4]	15	1			T12	4		T34	1		T47	1
auto[1]	values[5]	values[5]	7	1			T134	1		T240	1		T272	1
auto[1]	values[5]	values[6]	8	1			T41	1		T47	1		T193	2
auto[1]	values[5]	values[7]	3	1			T39	2		T188	1		-	-
auto[1]	values[6]	values[0]	12	1			T134	2		T135	1		T188	1
auto[1]	values[6]	values[1]	15	1			T40	1		T134	3		T135	2
auto[1]	values[6]	values[2]	12	1			T40	1		T47	3		T193	3
auto[1]	values[6]	values[3]	14	1			T12	2		T34	2		T40	3
auto[1]	values[6]	values[4]	8	1			T245	2		T273	1		T274	1
auto[1]	values[6]	values[5]	9	1			T41	2		T60	2		T239	1
auto[1]	values[6]	values[6]	6	1			T135	1		T262	1		T52	4
auto[1]	values[6]	values[7]	12	1			T245	2		T196	3		T266	2
auto[1]	values[7]	values[0]	10	1			T42	2		T218	2		T275	1
auto[1]	values[7]	values[1]	8	1			T86	1		T199	1		T233	2
auto[1]	values[7]	values[2]	5	1			T266	1		T236	2		T50	1
auto[1]	values[7]	values[3]	6	1			T34	1		T218	1		T47	1
auto[1]	values[7]	values[4]	15	1			T47	1		T273	2		T255	4
auto[1]	values[7]	values[5]	7	1			T188	1		T255	3		T233	1
auto[1]	values[7]	values[6]	4	1			T12	2		T189	2		-	-
auto[1]	values[7]	values[7]	7	1			T185	1		T188	1		T257	1