Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2590

1

T11

21

T12

5

T14

5

auto[1]

2819

1

T11

28

T12

7

T14

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2867

1

T12

12

T14

8

T15

4

auto[1]

2542

1

T11

49

T15

7

T16

60

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4275

1

T11

49

T12

8

T14

7

auto[1]

1134

1

T12

4

T14

1

T15

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1082	1			T11	14		T12	1		T14	3
valid[1]	1079	1			T11	8		T12	4		T14	2
valid[2]	1113	1			T11	10		T12	2		T14	1
valid[3]	1075	1			T11	9		T12	1		T14	1
valid[4]	1060	1			T11	8		T12	4		T14	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	173	1			T12	1		T14	2		T15	1
auto[0]	auto[0]	valid[0]	auto[1]	241	1			T11	7		T15	2		T16	5
auto[0]	auto[0]	valid[1]	auto[0]	156	1			T12	2		T14	1		T18	1
auto[0]	auto[0]	valid[1]	auto[1]	230	1			T11	2		T16	6		T44	3
auto[0]	auto[0]	valid[2]	auto[0]	187	1			T12	1		T34	7		T64	1
auto[0]	auto[0]	valid[2]	auto[1]	226	1			T11	6		T16	3		T286	7
auto[0]	auto[0]	valid[3]	auto[0]	159	1			T27	1		T28	1		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	254	1			T11	3		T15	2		T16	6
auto[0]	auto[0]	valid[4]	auto[0]	144	1			T14	1		T17	1		T18	1
auto[0]	auto[0]	valid[4]	auto[1]	250	1			T11	3		T16	9		T44	1
auto[0]	auto[1]	valid[0]	auto[0]	182	1			T17	2		T28	1		T33	3
auto[0]	auto[1]	valid[0]	auto[1]	255	1			T11	7		T16	4		T44	1
auto[0]	auto[1]	valid[1]	auto[0]	205	1			T14	1		T18	1		T19	1
auto[0]	auto[1]	valid[1]	auto[1]	274	1			T11	6		T16	5		T44	1
auto[0]	auto[1]	valid[2]	auto[0]	190	1			T12	1		T14	1		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	270	1			T11	4		T15	1		T16	7
auto[0]	auto[1]	valid[3]	auto[0]	156	1			T14	1		T33	3		T34	4
auto[0]	auto[1]	valid[3]	auto[1]	271	1			T11	6		T15	1		T16	9
auto[0]	auto[1]	valid[4]	auto[0]	181	1			T12	3		T15	2		T19	2
auto[0]	auto[1]	valid[4]	auto[1]	271	1			T11	5		T15	1		T16	6
auto[1]	auto[0]	valid[0]	auto[0]	127	1			T14	1		T28	2		T33	1
auto[1]	auto[0]	valid[1]	auto[0]	107	1			T28	1		T33	1		T97	1
auto[1]	auto[0]	valid[2]	auto[0]	115	1			T19	1		T27	1		T33	1
auto[1]	auto[0]	valid[3]	auto[0]	121	1			T15	1		T27	1		T28	1
auto[1]	auto[0]	valid[4]	auto[0]	100	1			T12	1		T28	1		T33	1
auto[1]	auto[1]	valid[0]	auto[0]	104	1			T28	1		T33	1		T34	1
auto[1]	auto[1]	valid[1]	auto[0]	107	1			T12	2		T18	2		T19	2
auto[1]	auto[1]	valid[2]	auto[0]	125	1			T19	1		T34	3		T64	2
auto[1]	auto[1]	valid[3]	auto[0]	114	1			T12	1		T19	1		T34	1
auto[1]	auto[1]	valid[4]	auto[0]	114	1			T17	1		T19	1		T27	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal