Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73137

1

T12

407

T14

231

T15

232

auto[1]

25614

1

T11

546

T15

41

T16

722

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71892

1

T11

546

T12

269

T14

157

auto[1]

26859

1

T12

138

T14

74

T15

83

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	50887	1			T11	273		T12	200		T14	118
others[1]	8301	1			T11	47		T12	37		T14	14
others[2]	8404	1			T11	49		T12	40		T14	19
others[3]	9486	1			T11	65		T12	45		T14	26
interest[1]	5384	1			T11	27		T12	24		T14	21
interest[4]	33376	1			T11	180		T12	133		T14	69
interest[64]	16289	1			T11	85		T12	61		T14	33

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23713	1			T12	137		T14	82		T15	74
auto[0]	auto[0]	others[1]	3836	1			T12	24		T14	9		T15	10
auto[0]	auto[0]	others[2]	3949	1			T12	23		T14	13		T15	10
auto[0]	auto[0]	others[3]	4650	1			T12	26		T14	17		T15	13
auto[0]	auto[0]	interest[1]	2502	1			T12	18		T14	15		T15	9
auto[0]	auto[0]	interest[4]	15471	1			T12	92		T14	49		T15	52
auto[0]	auto[0]	interest[64]	7628	1			T12	41		T14	21		T15	33
auto[0]	auto[1]	others[0]	13343	1			T11	273		T15	27		T16	348
auto[0]	auto[1]	others[1]	2195	1			T11	47		T16	65		T19	2
auto[0]	auto[1]	others[2]	2168	1			T11	49		T15	4		T16	52
auto[0]	auto[1]	others[3]	2279	1			T11	65		T15	4		T16	75
auto[0]	auto[1]	interest[1]	1408	1			T11	27		T15	3		T16	48
auto[0]	auto[1]	interest[4]	8895	1			T11	180		T15	16		T16	231
auto[0]	auto[1]	interest[64]	4221	1			T11	85		T15	3		T16	134
auto[1]	auto[0]	others[0]	13831	1			T12	63		T14	36		T15	39
auto[1]	auto[0]	others[1]	2270	1			T12	13		T14	5		T15	8
auto[1]	auto[0]	others[2]	2287	1			T12	17		T14	6		T15	7
auto[1]	auto[0]	others[3]	2557	1			T12	19		T14	9		T15	4
auto[1]	auto[0]	interest[1]	1474	1			T12	6		T14	6		T15	4
auto[1]	auto[0]	interest[4]	9010	1			T12	41		T14	20		T15	26
auto[1]	auto[0]	interest[64]	4440	1			T12	20		T14	12		T15	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal