Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	745	1			T18	20		T69	20		T71	18
all_values[1]	745	1			T18	20		T69	20		T71	18
all_values[2]	745	1			T18	20		T69	20		T71	18
all_values[3]	745	1			T18	20		T69	20		T71	18
all_values[4]	745	1			T18	20		T69	20		T71	18
all_values[5]	745	1			T18	20		T69	20		T71	18
all_values[6]	745	1			T18	20		T69	20		T71	18
all_values[7]	745	1			T18	20		T69	20		T71	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3211

1

T18

71

T69

68

T71

80

auto[1]

2749

1

T18

89

T69

92

T71

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2462

1

T18

68

T69

71

T71

72

auto[1]

3498

1

T18

92

T69

89

T71

72

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3510

1

T18

91

T69

96

T71

91

auto[1]

2450

1

T18

69

T69

64

T71

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	148	1			T18	2		T69	2		T71	4
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T18	4		T69	3		T71	1
all_values[0]	auto[0]	auto[1]	auto[0]	154	1			T18	5		T69	6		T71	2
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T18	1		T69	1		T71	4
all_values[0]	auto[1]	auto[0]	auto[1]	163	1			T18	3		T69	3		T71	3
all_values[0]	auto[1]	auto[1]	auto[1]	129	1			T18	5		T69	5		T71	4
all_values[1]	auto[0]	auto[0]	auto[0]	181	1			T18	4		T69	2		T71	5
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T18	1		T71	3		T161	1
all_values[1]	auto[0]	auto[1]	auto[0]	115	1			T18	3		T69	3		T71	3
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T18	2		T69	4		T71	1
all_values[1]	auto[1]	auto[0]	auto[1]	162	1			T18	3		T71	3		T161	1
all_values[1]	auto[1]	auto[1]	auto[1]	132	1			T18	7		T69	11		T71	3
all_values[2]	auto[0]	auto[0]	auto[0]	150	1			T18	5		T69	4		T71	4
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T18	1		T69	1		T161	1
all_values[2]	auto[0]	auto[1]	auto[0]	107	1			T18	2		T69	4		T71	6
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T18	3		T69	2		T71	2
all_values[2]	auto[1]	auto[0]	auto[1]	179	1			T18	3		T69	6		T71	5
all_values[2]	auto[1]	auto[1]	auto[1]	137	1			T18	6		T69	3		T71	1
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T18	1		T69	8		T71	9
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T18	1		T69	3		T71	2
all_values[3]	auto[0]	auto[1]	auto[0]	106	1			T18	8		T69	2		T165	4
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T18	2		T69	1		T71	1
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T18	1		T69	2		T71	6
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T18	7		T69	4		T161	1
all_values[4]	auto[0]	auto[0]	auto[0]	169	1			T18	6		T69	3		T71	2
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T18	1		T69	4		T71	1
all_values[4]	auto[0]	auto[1]	auto[0]	159	1			T18	2		T69	6		T71	2
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T71	1		T166	2		T152	1
all_values[4]	auto[1]	auto[0]	auto[1]	158	1			T18	4		T69	5		T71	7
all_values[4]	auto[1]	auto[1]	auto[1]	137	1			T18	7		T69	2		T71	5
all_values[5]	auto[0]	auto[0]	auto[0]	245	1			T18	6		T69	3		T71	7
all_values[5]	auto[0]	auto[1]	auto[0]	200	1			T18	6		T69	9		T71	3
all_values[5]	auto[1]	auto[0]	auto[1]	156	1			T18	2		T69	5		T71	5
all_values[5]	auto[1]	auto[1]	auto[1]	144	1			T18	6		T69	3		T71	3
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T18	8		T69	3		T71	1
all_values[6]	auto[0]	auto[0]	auto[1]	59	1			T69	1		T166	1		T152	1
all_values[6]	auto[0]	auto[1]	auto[0]	133	1			T18	4		T69	7		T71	10
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T18	3		T69	2		T71	2
all_values[6]	auto[1]	auto[0]	auto[1]	175	1			T18	4		T69	1		T71	5
all_values[6]	auto[1]	auto[1]	auto[1]	135	1			T18	1		T69	6		T161	1
all_values[7]	auto[0]	auto[0]	auto[0]	145	1			T18	4		T69	2		T71	5
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T18	2		T69	2		T71	1
all_values[7]	auto[0]	auto[1]	auto[0]	134	1			T18	2		T69	7		T71	9
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T18	2		T69	1		T166	2
all_values[7]	auto[1]	auto[0]	auto[1]	187	1			T18	5		T69	5		T71	1
all_values[7]	auto[1]	auto[1]	auto[1]	137	1			T18	5		T69	3		T71	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal