Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7676995	1			T1	1		T2	166		T3	1
all_values[1]	7676995	1			T1	1		T2	166		T3	1
all_values[2]	7676995	1			T1	1		T2	166		T3	1
all_values[3]	7676995	1			T1	1		T2	166		T3	1
all_values[4]	7676995	1			T1	1		T2	166		T3	1
all_values[5]	7676995	1			T1	1		T2	166		T3	1
all_values[6]	7676995	1			T1	1		T2	166		T3	1
all_values[7]	7676995	1			T1	1		T2	166		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59503300

1

T1

8

T2

1328

T3

8

auto[1]

1912660

1

T35

15334

T69

56

T46

218256

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61338311

1

T1

8

T2

1328

T3

8

auto[1]

77649

1

T7

3

T9

305

T11

399

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7524370	1			T1	1		T2	166		T3	1
all_values[0]	auto[0]	auto[1]	45383	1			T9	159		T11	199		T17	64
all_values[0]	auto[1]	auto[0]	106139	1			T69	6		T46	36343		T137	8
all_values[0]	auto[1]	auto[1]	1103	1			T35	1		T69	1		T46	32
all_values[1]	auto[0]	auto[0]	7365493	1			T1	1		T2	166		T3	1
all_values[1]	auto[0]	auto[1]	20122	1			T9	105		T11	151		T17	2
all_values[1]	auto[1]	auto[0]	290001	1			T35	2		T69	3		T46	36349
all_values[1]	auto[1]	auto[1]	1379	1			T35	2		T69	5		T46	26
all_values[2]	auto[0]	auto[0]	7416152	1			T1	1		T2	166		T3	1
all_values[2]	auto[0]	auto[1]	7286	1			T9	41		T11	49		T22	19
all_values[2]	auto[1]	auto[0]	253163	1			T35	3830		T69	4		T46	2
all_values[2]	auto[1]	auto[1]	394	1			T35	3		T69	3		T46	1
all_values[3]	auto[0]	auto[0]	7397501	1			T1	1		T2	166		T3	1
all_values[3]	auto[0]	auto[1]	172	1			T35	3		T69	6		T46	1
all_values[3]	auto[1]	auto[0]	279140	1			T35	1		T69	3		T46	36373
all_values[3]	auto[1]	auto[1]	182	1			T35	2		T69	4		T46	1
all_values[4]	auto[0]	auto[0]	7367035	1			T1	1		T2	166		T3	1
all_values[4]	auto[0]	auto[1]	189	1			T134	2		T35	3		T69	3
all_values[4]	auto[1]	auto[0]	309597	1			T35	1		T69	3		T46	36372
all_values[4]	auto[1]	auto[1]	174	1			T35	2		T69	4		T46	3
all_values[5]	auto[0]	auto[0]	7558729	1			T1	1		T2	166		T3	1
all_values[5]	auto[0]	auto[1]	433	1			T7	3		T56	2		T183	12
all_values[5]	auto[1]	auto[0]	117682	1			T35	3829		T69	5		T46	36373
all_values[5]	auto[1]	auto[1]	151	1			T35	1		T69	2		T46	3
all_values[6]	auto[0]	auto[0]	7405374	1			T1	1		T2	166		T3	1
all_values[6]	auto[0]	auto[1]	160	1			T35	2		T69	5		T137	6
all_values[6]	auto[1]	auto[0]	271271	1			T35	3827		T69	1		T46	36374
all_values[6]	auto[1]	auto[1]	190	1			T35	2		T69	1		T46	2
all_values[7]	auto[0]	auto[0]	7394743	1			T1	1		T2	166		T3	1
all_values[7]	auto[0]	auto[1]	158	1			T35	3		T69	2		T46	1
all_values[7]	auto[1]	auto[0]	281921	1			T35	3826		T69	7		T46	1
all_values[7]	auto[1]	auto[1]	173	1			T35	5		T69	4		T46	1