Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	40467	1			T2	76		T3	16		T9	445
auto[SpiFlashAddrCfg]	9547	1			T2	2		T4	13		T9	39
auto[SpiFlashAddr3b]	11300	1			T2	8		T9	81		T11	48
auto[SpiFlashAddr4b]	9533	1			T9	39		T11	19		T13	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40825

1

T2

86

T3

16

T4

13

auto[1]

30022

1

T9

347

T11

87

T17

41

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37626

1

T2

72

T3

16

T4

6

auto[1]

33221

1

T2

14

T4

7

T9

320

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	46178	1			T2	78		T3	16		T9	476
values[1]	1285	1			T9	6		T11	1		T17	7
values[2]	1792	1			T2	2		T9	10		T11	7
values[3]	1736	1			T9	13		T11	2		T12	2
values[4]	1929	1			T9	7		T11	5		T17	8
values[5]	1875	1			T2	2		T9	11		T11	8
values[6]	1783	1			T9	5		T11	11		T22	8
values[7]	1924	1			T9	8		T11	8		T17	5
values[8]	12345	1			T2	4		T4	13		T9	68

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33391

1

T2

86

T3

16

T10

8

auto[1]

37456

1

T4

13

T9

604

T11

223

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

68302

1

T2

84

T3

16

T4

13

write

2545

1

T2

2

T9

11

T11

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24925

1

T2

10

T3

16

T4

13

valids[0x1]

45922

1

T2

76

T9

471

T11

117

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1935	1			T2	10		T9	8		T11	3
internal_process_ops[0x5a]	1889	1			T9	13		T11	3		T21	2
internal_process_ops[0x05]	23271	1			T2	64		T9	353		T11	49
internal_process_ops[0x35]	1884	1			T9	3		T11	7		T12	4
internal_process_ops[0x15]	1990	1			T9	20		T11	6		T17	2
internal_process_ops[0x03]	1290	1			T9	5		T11	6		T17	1
internal_process_ops[0x0b]	1368	1			T9	5		T11	3		T13	2
internal_process_ops[0x3b]	1335	1			T2	2		T9	7		T11	4
internal_process_ops[0x6b]	1343	1			T9	2		T11	2		T12	2
internal_process_ops[0xbb]	1279	1			T4	6		T9	6		T11	4
internal_process_ops[0xeb]	1276	1			T4	7		T9	4		T11	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69559

1

T2

86

T3

16

T4

13

auto[1]

1288

1

T9

7

T11

8

T17

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68376

1

T2

84

T3

16

T4

13

auto[1]

2471

1

T2

2

T9

13

T11

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11381

1

T2

76

T3

16

T10

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6345

1

T33

8

T29

13

T34

446

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2458

1

T2

2

T13

4

T32

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2122

1

T29

2

T34

30

T35

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2983

1

T2

6

T12

6

T13

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2396

1

T33

2

T29

2

T34

39

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2477

1

T13

2

T40

14

T41

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2140

1

T33

14

T29

5

T34

35

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T13

6

T34

3

T45

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T34

5

T35

2

T45

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T35

1

T37

2

T178

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

77

1

T35

1

T44

4

T45

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

93

1

T44

2

T45

2

T49

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T45

3

T46

3

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

62

1

T34

3

T35

2

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

60

1

T34

2

T45

3

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

66

1

T2

2

T34

2

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T34

1

T37

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

41

1

T37

1

T44

1

T45

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T33

2

T34

1

T45

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

77

1

T29

1

T34

1

T37

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T34

1

T35

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T29

1

T34

1

T37

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

65

1

T33

2

T34

1

T48

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13057

1

T9

179

T11

88

T17

43

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9020

1

T9

262

T11

23

T17

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2305

1

T4

13

T9

21

T11

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2024

1

T9

17

T11

22

T17

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2707

1

T9

42

T11

24

T17

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2610

1

T9

36

T11

23

T17

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2197

1

T9

11

T11

9

T17

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2080

1

T9

25

T11

7

T17

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T11

1

T30

3

T135

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

83

1

T9

2

T30

3

T51

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T9

1

T11

3

T22

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T9

1

T11

3

T22

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T179

1

T95

1

T94

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T51

3

T93

4

T94

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T9

1

T22

1

T51

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T11

3

T22

2

T30

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

71

1

T30

2

T51

2

T95

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T30

2

T35

2

T135

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T9

2

T51

1

T92

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T9

1

T11

1

T30

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

81

1

T17

1

T31

2

T51

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

76

1

T9

2

T11

1

T51

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T11

2

T17

1

T30

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T9

1

T17

1

T51

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4625	1			T2	2		T3	16		T10	8
auto[0]	values[0]	valids[0x1]	16119	1			T2	76		T12	4		T13	6
auto[0]	values[1]	valids[0x1]	574	1			T42	2		T34	7		T35	1
auto[0]	values[2]	valids[0x0]	616	1			T2	2		T13	2		T29	2
auto[0]	values[2]	valids[0x1]	331	1			T40	2		T34	12		T35	4
auto[0]	values[3]	valids[0x0]	574	1			T12	2		T34	10		T35	4
auto[0]	values[3]	valids[0x1]	305	1			T34	5		T35	1		T37	2
auto[0]	values[4]	valids[0x0]	680	1			T34	13		T35	1		T37	3
auto[0]	values[4]	valids[0x1]	312	1			T34	10		T35	4		T37	4
auto[0]	values[5]	valids[0x0]	580	1			T2	2		T41	2		T29	1
auto[0]	values[5]	valids[0x1]	367	1			T43	6		T38	2		T34	4
auto[0]	values[6]	valids[0x0]	618	1			T33	6		T29	1		T43	2
auto[0]	values[6]	valids[0x1]	319	1			T34	8		T37	4		T180	2
auto[0]	values[7]	valids[0x0]	648	1			T33	6		T29	2		T34	12
auto[0]	values[7]	valids[0x1]	358	1			T34	5		T35	1		T181	4
auto[0]	values[8]	valids[0x0]	4044	1			T2	4		T12	4		T13	14
auto[0]	values[8]	valids[0x1]	2321	1			T13	4		T21	2		T182	4
auto[1]	values[0]	valids[0x0]	5760	1			T9	53		T11	49		T17	24
auto[1]	values[0]	valids[0x1]	19674	1			T9	423		T11	87		T17	44
auto[1]	values[1]	valids[0x1]	711	1			T9	6		T11	1		T17	7
auto[1]	values[2]	valids[0x0]	519	1			T9	7		T11	5		T17	2
auto[1]	values[2]	valids[0x1]	326	1			T9	3		T11	2		T17	1
auto[1]	values[3]	valids[0x0]	554	1			T9	5		T11	2		T17	2
auto[1]	values[3]	valids[0x1]	303	1			T9	8		T17	4		T31	1
auto[1]	values[4]	valids[0x0]	563	1			T9	7		T11	5		T17	2
auto[1]	values[4]	valids[0x1]	374	1			T17	6		T22	1		T30	2
auto[1]	values[5]	valids[0x0]	571	1			T9	7		T11	4		T22	5
auto[1]	values[5]	valids[0x1]	357	1			T9	4		T11	4		T17	2
auto[1]	values[6]	valids[0x0]	505	1			T9	4		T11	8		T22	6
auto[1]	values[6]	valids[0x1]	341	1			T9	1		T11	3		T22	2
auto[1]	values[7]	valids[0x0]	564	1			T9	5		T11	7		T22	5
auto[1]	values[7]	valids[0x1]	354	1			T9	3		T11	1		T17	5
auto[1]	values[8]	valids[0x0]	3504	1			T4	13		T9	45		T11	26
auto[1]	values[8]	valids[0x1]	2476	1			T9	23		T11	19		T17	4