Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19963

1

T2

3

T3

25

T4

12

auto[1]

23577

1

T2

66

T9

357

T11

57

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16759

1

T2

5

T3

25

T4

12

auto[1]

26781

1

T2

64

T9

376

T11

62

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7085	1			T2	69		T3	6		T4	1
auto[524288:1048575]	5463	1			T9	113		T10	2		T11	45
auto[1048576:1572863]	5064	1			T4	3		T9	11		T11	2
auto[1572864:2097151]	5094	1			T3	9		T9	82		T11	2
auto[2097152:2621439]	4990	1			T4	2		T9	100		T11	6
auto[2621440:3145727]	5372	1			T3	7		T8	2		T9	7
auto[3145728:3670015]	5445	1			T3	2		T4	3		T9	8
auto[3670016:4194303]	5027	1			T3	1		T4	3		T9	96

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42677

1

T2

69

T3

25

T4

12

auto[1]

863

1

T9

10

T11

1

T17

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34988

1

T2

69

T3

25

T4

12

auto[1]

8552

1

T9

36

T11

36

T22

51

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1984	1			T2	3		T3	6		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	755	1			T9	4		T21	2		T17	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1409	1			T9	5		T10	2		T11	14
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	482	1			T9	2		T11	3		T29	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1402	1			T4	3		T9	5		T11	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	584	1			T9	5		T11	1		T17	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1304	1			T3	9		T9	7		T11	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	506	1			T9	2		T11	1		T30	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1376	1			T4	2		T9	8		T11	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	552	1			T9	3		T11	1		T21	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1359	1			T3	7		T8	2		T9	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	544	1			T9	4		T11	3		T39	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1416	1			T3	2		T4	3		T9	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	523	1			T9	3		T11	5		T17	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1388	1			T3	1		T4	3		T9	15
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	509	1			T9	4		T17	3		T22	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	384	1			T9	5		T22	1		T34	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	165	1			T9	2		T51	1		T34	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	336	1			T11	4		T51	2		T34	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	146	1			T11	2		T22	1		T51	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	322	1			T34	3		T37	2		T135	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	167	1			T9	1		T34	2		T37	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	334	1			T9	2		T30	2		T34	11
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	150	1			T9	1		T30	2		T51	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	275	1			T9	2		T11	2		T22	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	132	1			T9	1		T11	1		T22	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	301	1			T11	2		T51	1		T34	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	138	1			T11	1		T35	3		T37	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	350	1			T11	5		T22	1		T30	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	167	1			T11	1		T30	1		T51	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	348	1			T11	6		T22	2		T29	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	155	1			T22	2		T29	3		T51	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	325	1			T2	2		T9	1		T17	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2917	1			T2	64		T9	17		T17	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	256	1			T9	2		T11	5		T29	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2342	1			T9	104		T11	17		T29	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	243	1			T30	3		T51	1		T34	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1823	1			T30	5		T51	17		T34	17
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	208	1			T9	3		T22	3		T30	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1830	1			T9	67		T22	87		T30	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	253	1			T9	1		T51	2		T34	7
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2001	1			T9	63		T51	3		T34	157
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	227	1			T11	1		T34	2		T37	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2185	1			T11	2		T34	9		T37	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	257	1			T11	4		T17	3		T51	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2020	1			T11	13		T17	5		T51	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	235	1			T9	4		T11	1		T17	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1773	1			T9	73		T11	2		T17	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	66	1			T34	3		T35	1		T37	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	489	1			T34	74		T35	5		T37	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	55	1			T35	1		T37	1		T44	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	437	1			T35	2		T37	7		T44	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	58	1			T34	1		T101	1		T44	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	465	1			T34	20		T101	1		T44	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	62	1			T30	1		T34	2		T35	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	700	1			T30	3		T34	58		T35	41
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	42	1			T9	2		T51	1		T44	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	359	1			T9	20		T51	2		T44	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T37	1		T94	2		T210	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	570	1			T37	1		T94	110		T210	29
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	68	1			T11	1		T135	2		T136	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	644	1			T11	2		T135	4		T136	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	68	1			T11	2		T22	1		T29	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	551	1			T11	7		T22	32		T29	8

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15734	1			T2	3		T3	25		T4	12
auto[0]	auto[0]	auto[1]	359	1			T9	6		T17	1		T22	2
auto[0]	auto[1]	auto[0]	3785	1			T9	13		T11	24		T22	18
auto[0]	auto[1]	auto[1]	85	1			T9	1		T34	3		T35	1
auto[1]	auto[0]	auto[0]	18547	1			T2	66		T9	332		T11	44
auto[1]	auto[0]	auto[1]	348	1			T9	3		T11	1		T29	2
auto[1]	auto[1]	auto[0]	4611	1			T9	22		T11	12		T22	33
auto[1]	auto[1]	auto[1]	71	1			T29	1		T34	1		T35	1