Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19879

1

T2

86

T3

16

T10

8

auto[1]

13512

1

T33

28

T29

23

T34

558

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4278	1			T12	10		T182	6		T34	153
values[1]	3685	1			T10	8		T13	26		T39	22
values[2]	4865	1			T33	28		T34	150		T37	23
values[3]	3632	1			T3	16		T34	110		T35	134
values[4]	4246	1			T29	29		T38	12		T34	59
values[5]	4057	1			T2	86		T42	2		T43	22
values[6]	4198	1			T21	6		T36	51		T34	106
values[7]	4430	1			T32	6		T40	22		T34	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4698	1			T2	86		T12	10		T34	170
values[1]	5400	1			T10	8		T13	26		T32	6
values[2]	4136	1			T3	16		T41	24		T34	20
values[3]	3561	1			T29	66		T43	22		T38	12
values[4]	3990	1			T33	28		T50	10		T34	81
values[5]	3746	1			T39	22		T40	22		T182	6
values[6]	4520	1			T36	51		T34	190		T35	21
values[7]	3340	1			T34	20		T35	42		T37	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	296	1			T12	10		T34	54		T207	12
auto[0]	values[0]	values[1]	294	1			T44	12		T45	18		T178	12
auto[0]	values[0]	values[2]	272	1			T44	14		T211	12		T250	8
auto[0]	values[0]	values[3]	243	1			T35	15		T24	11		T201	48
auto[0]	values[0]	values[4]	253	1			T37	26		T45	11		T200	13
auto[0]	values[0]	values[5]	344	1			T182	6		T34	21		T44	14
auto[0]	values[0]	values[6]	304	1			T34	25		T137	9		T49	12
auto[0]	values[0]	values[7]	285	1			T37	14		T251	10		T197	50
auto[0]	values[1]	values[0]	507	1			T233	18		T200	14		T204	29
auto[0]	values[1]	values[1]	426	1			T10	8		T13	26		T34	9
auto[0]	values[1]	values[2]	180	1			T41	24		T137	12		T49	22
auto[0]	values[1]	values[3]	171	1			T29	29		T34	13		T178	11
auto[0]	values[1]	values[4]	311	1			T44	13		T252	4		T178	7
auto[0]	values[1]	values[5]	286	1			T39	22		T34	9		T253	4
auto[0]	values[1]	values[6]	243	1			T46	13		T200	8		T217	11
auto[0]	values[1]	values[7]	131	1			T254	6		T49	15		T178	12
auto[0]	values[2]	values[0]	165	1			T46	16		T49	10		T195	6
auto[0]	values[2]	values[1]	396	1			T34	12		T217	13		T193	30
auto[0]	values[2]	values[2]	446	1			T178	27		T196	16		T255	59
auto[0]	values[2]	values[3]	513	1			T34	17		T37	14		T45	8
auto[0]	values[2]	values[4]	314	1			T211	13		T200	15		T217	16
auto[0]	values[2]	values[5]	408	1			T45	17		T204	12		T256	123
auto[0]	values[2]	values[6]	348	1			T34	11		T45	10		T242	32
auto[0]	values[2]	values[7]	206	1			T47	6		T24	9		T82	11
auto[0]	values[3]	values[0]	358	1			T34	11		T35	10		T45	9
auto[0]	values[3]	values[1]	353	1			T45	37		T228	14		T172	8
auto[0]	values[3]	values[2]	210	1			T3	16		T35	14		T200	10
auto[0]	values[3]	values[3]	157	1			T37	11		T172	13		T257	10
auto[0]	values[3]	values[4]	305	1			T45	17		T178	20		T197	46
auto[0]	values[3]	values[5]	180	1			T212	16		T214	8		T207	14
auto[0]	values[3]	values[6]	287	1			T205	16		T45	13		T46	11
auto[0]	values[3]	values[7]	315	1			T258	12		T259	10		T207	8
auto[0]	values[4]	values[0]	361	1			T208	130		T211	13		T204	14
auto[0]	values[4]	values[1]	328	1			T34	26		T35	13		T47	19
auto[0]	values[4]	values[2]	375	1			T34	11		T37	10		T45	25
auto[0]	values[4]	values[3]	247	1			T29	14		T38	12		T46	16
auto[0]	values[4]	values[4]	380	1			T171	12		T196	14		T260	9
auto[0]	values[4]	values[5]	393	1			T181	12		T137	12		T261	12
auto[0]	values[4]	values[6]	309	1			T35	13		T49	10		T178	13
auto[0]	values[4]	values[7]	207	1			T35	19		T262	22		T236	11
auto[0]	values[5]	values[0]	419	1			T2	86		T137	11		T200	31
auto[0]	values[5]	values[1]	289	1			T34	13		T44	13		T263	2
auto[0]	values[5]	values[2]	205	1			T91	12		T204	9		T217	14
auto[0]	values[5]	values[3]	270	1			T43	22		T226	18		T196	12
auto[0]	values[5]	values[4]	357	1			T50	10		T227	28		T230	4
auto[0]	values[5]	values[5]	195	1			T42	2		T264	6		T178	12
auto[0]	values[5]	values[6]	314	1			T37	25		T137	12		T265	6
auto[0]	values[5]	values[7]	434	1			T34	11		T44	9		T266	4
auto[0]	values[6]	values[0]	357	1			T207	24		T194	9		T260	10
auto[0]	values[6]	values[1]	453	1			T21	6		T34	9		T37	12
auto[0]	values[6]	values[2]	210	1			T244	4		T45	10		T172	6
auto[0]	values[6]	values[3]	220	1			T44	10		T178	11		T169	4
auto[0]	values[6]	values[4]	289	1			T34	11		T37	15		T243	36
auto[0]	values[6]	values[5]	359	1			T109	8		T217	22		T267	32
auto[0]	values[6]	values[6]	307	1			T36	51		T44	21		T49	9
auto[0]	values[6]	values[7]	236	1			T47	12		T178	9		T24	18
auto[0]	values[7]	values[0]	369	1			T199	16		T200	9		T197	8
auto[0]	values[7]	values[1]	651	1			T32	6		T37	12		T45	48
auto[0]	values[7]	values[2]	420	1			T44	20		T45	13		T178	12
auto[0]	values[7]	values[3]	394	1			T34	13		T45	24		T204	10
auto[0]	values[7]	values[4]	152	1			T268	28		T49	6		T217	12
auto[0]	values[7]	values[5]	263	1			T40	22		T269	4		T232	11
auto[0]	values[7]	values[6]	420	1			T34	9		T37	30		T270	8
auto[0]	values[7]	values[7]	189	1			T44	17		T45	9		T49	22
auto[1]	values[0]	values[0]	139	1			T34	6		T207	8		T198	3
auto[1]	values[0]	values[1]	225	1			T44	13		T45	22		T178	8
auto[1]	values[0]	values[2]	258	1			T44	13		T211	64		T217	9
auto[1]	values[0]	values[3]	181	1			T35	7		T24	9		T201	11
auto[1]	values[0]	values[4]	307	1			T37	8		T45	9		T200	7
auto[1]	values[0]	values[5]	244	1			T34	8		T44	6		T45	5
auto[1]	values[0]	values[6]	440	1			T34	39		T137	19		T49	8
auto[1]	values[0]	values[7]	193	1			T37	6		T251	10		T197	4
auto[1]	values[1]	values[0]	173	1			T200	6		T204	10		T257	11
auto[1]	values[1]	values[1]	186	1			T34	11		T44	12		T211	4
auto[1]	values[1]	values[2]	84	1			T137	9		T49	6		T200	6
auto[1]	values[1]	values[3]	175	1			T29	8		T34	18		T178	9
auto[1]	values[1]	values[4]	168	1			T44	7		T178	13		T232	10
auto[1]	values[1]	values[5]	347	1			T34	69		T45	34		T46	10
auto[1]	values[1]	values[6]	223	1			T46	8		T200	12		T217	10
auto[1]	values[1]	values[7]	74	1			T49	7		T178	8		T217	14
auto[1]	values[2]	values[0]	100	1			T46	7		T49	11		T197	9
auto[1]	values[2]	values[1]	244	1			T34	8		T217	7		T196	10
auto[1]	values[2]	values[2]	445	1			T178	33		T196	7		T201	34
auto[1]	values[2]	values[3]	425	1			T34	7		T37	9		T45	50
auto[1]	values[2]	values[4]	219	1			T33	28		T211	7		T200	12
auto[1]	values[2]	values[5]	131	1			T45	3		T204	8		T271	13
auto[1]	values[2]	values[6]	362	1			T34	95		T45	12		T49	9
auto[1]	values[2]	values[7]	143	1			T47	14		T24	15		T82	14
auto[1]	values[3]	values[0]	444	1			T34	99		T35	11		T45	63
auto[1]	values[3]	values[1]	188	1			T45	7		T172	12		T200	10
auto[1]	values[3]	values[2]	165	1			T35	99		T200	16		T160	4
auto[1]	values[3]	values[3]	79	1			T37	9		T172	11		T257	17
auto[1]	values[3]	values[4]	142	1			T45	3		T178	10		T197	17
auto[1]	values[3]	values[5]	100	1			T207	6		T196	3		T24	11
auto[1]	values[3]	values[6]	212	1			T45	7		T46	9		T207	15
auto[1]	values[3]	values[7]	137	1			T207	32		T201	9		T272	11
auto[1]	values[4]	values[0]	277	1			T211	43		T204	6		T194	31
auto[1]	values[4]	values[1]	214	1			T34	13		T35	12		T47	6
auto[1]	values[4]	values[2]	318	1			T34	9		T37	14		T45	6
auto[1]	values[4]	values[3]	104	1			T29	15		T46	4		T200	8
auto[1]	values[4]	values[4]	216	1			T196	24		T260	15		T232	12
auto[1]	values[4]	values[5]	181	1			T137	8		T273	7		T274	6
auto[1]	values[4]	values[6]	192	1			T35	8		T49	18		T178	11
auto[1]	values[4]	values[7]	144	1			T35	23		T209	8		T236	9
auto[1]	values[5]	values[0]	144	1			T137	16		T200	7		T197	6
auto[1]	values[5]	values[1]	435	1			T34	63		T44	7		T200	6
auto[1]	values[5]	values[2]	161	1			T235	22		T204	11		T217	7
auto[1]	values[5]	values[3]	85	1			T196	8		T24	3		T236	10
auto[1]	values[5]	values[4]	154	1			T178	5		T200	9		T217	3
auto[1]	values[5]	values[5]	105	1			T178	8		T238	5		T274	9
auto[1]	values[5]	values[6]	224	1			T37	10		T180	26		T137	8
auto[1]	values[5]	values[7]	266	1			T34	9		T44	18		T49	8
auto[1]	values[6]	values[0]	278	1			T207	8		T194	11		T260	10
auto[1]	values[6]	values[1]	396	1			T34	16		T37	21		T200	13
auto[1]	values[6]	values[2]	146	1			T45	10		T48	16		T172	14
auto[1]	values[6]	values[3]	175	1			T44	10		T178	20		T200	13
auto[1]	values[6]	values[4]	258	1			T34	70		T37	9		T236	6
auto[1]	values[6]	values[5]	120	1			T217	26		T198	9		T236	9
auto[1]	values[6]	values[6]	190	1			T44	6		T49	11		T178	11
auto[1]	values[6]	values[7]	204	1			T47	15		T178	11		T24	2
auto[1]	values[7]	values[0]	311	1			T200	11		T197	40		T207	8
auto[1]	values[7]	values[1]	322	1			T37	8		T45	32		T49	11
auto[1]	values[7]	values[2]	241	1			T44	4		T45	17		T178	8
auto[1]	values[7]	values[3]	122	1			T34	7		T45	8		T204	10
auto[1]	values[7]	values[4]	165	1			T49	14		T217	8		T24	8
auto[1]	values[7]	values[5]	90	1			T232	9		T24	8		T202	3
auto[1]	values[7]	values[6]	145	1			T34	11		T37	10		T211	5
auto[1]	values[7]	values[7]	176	1			T44	6		T45	11		T49	22