Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	477	1			T12	4		T29	1		T34	4
auto[ReadAddrCrossIntoMailbox]	360	1			T29	2		T34	5		T35	1
auto[ReadAddrCrossOutOfMailbox]	354	1			T34	9		T35	4		T37	3
auto[ReadAddrCrossAllMailbox]	250	1			T35	1		T244	2		T44	3
auto[ReadAddrOutsideMailbox]	4100	1			T2	2		T12	2		T13	14

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2783

1

T2

1

T12

3

T13

7

auto[1]

2758

1

T2

1

T12

3

T13

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	889	1			T41	4		T29	3		T43	4
read_ops[0x0b]	970	1			T13	2		T40	2		T29	1
read_ops[0x3b]	939	1			T2	2		T12	4		T13	6
read_ops[0x6b]	963	1			T12	2		T13	2		T29	1
read_ops[0xbb]	879	1			T29	2		T38	4		T34	9
read_ops[0xeb]	901	1			T13	4		T41	4		T33	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T35	1		T45	1		T242	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T29	1		T35	1		T242	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T35	1		T242	2		T226	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T34	1		T242	2		T226	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T35	1		T37	1		T172	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T34	3		T45	2		T49	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T35	1		T44	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T178	2		T166	1		T217	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	326	1			T41	2		T29	2		T43	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T41	2		T43	2		T34	8
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T35	1		T45	1		T46	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T44	2		T199	2		T49	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T49	1		T178	2		T204	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T29	1		T34	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T266	1		T233	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T34	3		T35	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T242	1		T178	1		T211	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	33	1			T44	1		T242	1		T196	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	358	1			T13	1		T40	1		T34	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T13	1		T40	1		T34	13
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T12	2		T34	1		T205	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T12	2		T35	1		T205	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T37	1		T45	1		T275	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T49	1		T275	2		T257	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T35	1		T37	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T34	1		T45	1		T233	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T45	1		T242	1		T207	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T242	1		T49	1		T200	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	356	1			T2	1		T13	3		T33	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T2	1		T13	3		T33	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	52	1			T37	1		T44	1		T137	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T34	1		T200	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T200	1		T217	1		T257	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T29	1		T34	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T34	1		T35	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T45	1		T251	1		T197	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T45	1		T207	1		T198	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T49	1		T251	1		T197	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	367	1			T12	1		T13	1		T50	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	361	1			T12	1		T13	1		T50	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T35	1		T205	1		T244	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T34	2		T205	1		T244	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T242	1		T49	1		T200	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T34	1		T242	1		T226	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T44	1		T45	1		T200	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T172	1		T200	2		T198	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T244	1		T242	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T244	1		T242	1		T178	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T38	2		T34	6		T37	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T29	2		T38	2		T35	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T109	2		T37	1		T242	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T109	2		T242	1		T199	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T34	1		T109	1		T44	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T109	1		T44	1		T242	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T34	1		T200	1		T217	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T207	1		T257	1		T236	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T242	1		T233	2		T276	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T44	1		T242	1		T233	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T13	2		T41	2		T33	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T13	2		T41	2		T33	3