Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7676995	1			T1	1		T2	166		T3	1
all_pins[1]	7676995	1			T1	1		T2	166		T3	1
all_pins[2]	7676995	1			T1	1		T2	166		T3	1
all_pins[3]	7676995	1			T1	1		T2	166		T3	1
all_pins[4]	7676995	1			T1	1		T2	166		T3	1
all_pins[5]	7676995	1			T1	1		T2	166		T3	1
all_pins[6]	7676995	1			T1	1		T2	166		T3	1
all_pins[7]	7676995	1			T1	1		T2	166		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	61137899	1			T1	8		T2	1328		T3	8
values[0x1]	278061	1			T35	4184		T69	24		T46	37020
transitions[0x0=>0x1]	275651	1			T35	3737		T69	16		T46	36397
transitions[0x1=>0x0]	275667	1			T35	3737		T69	16		T46	36397

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7675846	1			T1	1		T2	166		T3	1
all_pins[0]	values[0x1]	1149	1			T35	1		T69	1		T46	35
all_pins[0]	transitions[0x0=>0x1]	1073	1			T35	1		T69	1		T46	7
all_pins[0]	transitions[0x1=>0x0]	1356	1			T35	2		T69	5		T137	3
all_pins[1]	values[0x0]	7675563	1			T1	1		T2	166		T3	1
all_pins[1]	values[0x1]	1432	1			T35	2		T69	5		T46	28
all_pins[1]	transitions[0x0=>0x1]	1137	1			T35	1		T69	3		T46	27
all_pins[1]	transitions[0x1=>0x0]	110	1			T35	2		T69	1		T137	4
all_pins[2]	values[0x0]	7676590	1			T1	1		T2	166		T3	1
all_pins[2]	values[0x1]	405	1			T35	3		T69	3		T46	1
all_pins[2]	transitions[0x0=>0x1]	368	1			T35	3		T69	2		T46	1
all_pins[2]	transitions[0x1=>0x0]	145	1			T35	2		T69	3		T46	1
all_pins[3]	values[0x0]	7676813	1			T1	1		T2	166		T3	1
all_pins[3]	values[0x1]	182	1			T35	2		T69	4		T46	1
all_pins[3]	transitions[0x0=>0x1]	136	1			T35	2		T69	1		T46	1
all_pins[3]	transitions[0x1=>0x0]	128	1			T35	2		T69	1		T46	3
all_pins[4]	values[0x0]	7676821	1			T1	1		T2	166		T3	1
all_pins[4]	values[0x1]	174	1			T35	2		T69	4		T46	3
all_pins[4]	transitions[0x0=>0x1]	139	1			T35	1		T69	2		T46	3
all_pins[4]	transitions[0x1=>0x0]	3645	1			T35	470		T46	597		T137	1
all_pins[5]	values[0x0]	7673315	1			T1	1		T2	166		T3	1
all_pins[5]	values[0x1]	3680	1			T35	471		T69	2		T46	597
all_pins[5]	transitions[0x0=>0x1]	1866	1			T35	29		T69	2		T46	4
all_pins[5]	transitions[0x1=>0x0]	269052	1			T35	3256		T69	1		T46	35761
all_pins[6]	values[0x0]	7406129	1			T1	1		T2	166		T3	1
all_pins[6]	values[0x1]	270866	1			T35	3698		T69	1		T46	36354
all_pins[6]	transitions[0x0=>0x1]	270818	1			T35	3696		T69	1		T46	36353
all_pins[6]	transitions[0x1=>0x0]	125	1			T35	3		T69	4		T137	2
all_pins[7]	values[0x0]	7676822	1			T1	1		T2	166		T3	1
all_pins[7]	values[0x1]	173	1			T35	5		T69	4		T46	1
all_pins[7]	transitions[0x0=>0x1]	114	1			T35	4		T69	4		T46	1
all_pins[7]	transitions[0x1=>0x0]	1106	1			T69	1		T46	35		T137	5