Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4177	1			T50	10		T38	12		T34	136
values[1]	4119	1			T21	6		T182	6		T36	51
values[2]	4581	1			T3	16		T39	22		T40	22
values[3]	3895	1			T12	10		T35	113		T258	12
values[4]	4060	1			T10	8		T43	22		T34	38
values[5]	3698	1			T13	26		T41	24		T42	2
values[6]	4471	1			T2	86		T29	66		T34	165
values[7]	4390	1			T32	6		T34	44		T35	68

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4498	1			T10	8		T32	6		T33	28
values[1]	3982	1			T34	135		T35	21		T37	20
values[2]	4537	1			T3	16		T29	37		T43	22
values[3]	4768	1			T29	29		T38	12		T34	161
values[4]	5003	1			T2	86		T42	2		T34	172
values[5]	3500	1			T13	26		T34	26		T35	25
values[6]	3251	1			T21	6		T39	22		T41	24
values[7]	3852	1			T12	10		T40	22		T182	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32858

1

T2

86

T3

16

T10

8

auto[1]

533

1

T33

4

T34

11

T35

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	620	1			T50	10		T200	20		T207	23
auto[0]	values[0]	values[1]	663	1			T37	20		T45	40		T49	20
auto[0]	values[0]	values[2]	687	1			T181	12		T37	33		T45	40
auto[0]	values[0]	values[3]	302	1			T38	12		T34	31		T44	46
auto[0]	values[0]	values[4]	824	1			T34	81		T228	14		T137	28
auto[0]	values[0]	values[5]	437	1			T257	20		T236	19		T277	45
auto[0]	values[0]	values[6]	284	1			T34	20		T244	4		T278	16
auto[0]	values[0]	values[7]	303	1			T37	20		T44	20		T203	34
auto[0]	values[1]	values[0]	625	1			T45	38		T235	22		T263	2
auto[0]	values[1]	values[1]	497	1			T200	20		T232	24		T279	18
auto[0]	values[1]	values[2]	339	1			T211	39		T200	20		T217	21
auto[0]	values[1]	values[3]	528	1			T37	24		T233	18		T49	20
auto[0]	values[1]	values[4]	714	1			T34	49		T49	29		T217	22
auto[0]	values[1]	values[5]	337	1			T204	19		T207	20		T232	20
auto[0]	values[1]	values[6]	549	1			T21	6		T36	51		T178	20
auto[0]	values[1]	values[7]	458	1			T182	6		T44	24		T137	19
auto[0]	values[2]	values[0]	699	1			T33	24		T34	98		T37	40
auto[0]	values[2]	values[1]	573	1			T34	75		T45	43		T197	74
auto[0]	values[2]	values[2]	635	1			T3	16		T34	108		T37	19
auto[0]	values[2]	values[3]	585	1			T37	24		T212	16		T46	18
auto[0]	values[2]	values[4]	567	1			T137	47		T217	20		T201	53
auto[0]	values[2]	values[5]	288	1			T207	24		T196	20		T236	29
auto[0]	values[2]	values[6]	558	1			T39	22		T204	19		T217	20
auto[0]	values[2]	values[7]	616	1			T40	22		T109	8		T200	24
auto[0]	values[3]	values[0]	396	1			T35	111		T172	22		T200	26
auto[0]	values[3]	values[1]	437	1			T49	28		T197	68		T280	26
auto[0]	values[3]	values[2]	390	1			T240	8		T48	10		T200	20
auto[0]	values[3]	values[3]	861	1			T45	22		T195	6		T194	41
auto[0]	values[3]	values[4]	565	1			T258	12		T281	8		T197	24
auto[0]	values[3]	values[5]	401	1			T44	20		T49	40		T178	20
auto[0]	values[3]	values[6]	407	1			T282	30		T201	20		T236	20
auto[0]	values[3]	values[7]	364	1			T12	10		T44	25		T270	8
auto[0]	values[4]	values[0]	509	1			T10	8		T44	23		T178	39
auto[0]	values[4]	values[1]	329	1			T44	20		T251	20		T204	20
auto[0]	values[4]	values[2]	482	1			T43	22		T37	35		T178	51
auto[0]	values[4]	values[3]	842	1			T45	20		T217	20		T198	51
auto[0]	values[4]	values[4]	546	1			T34	38		T35	22		T91	12
auto[0]	values[4]	values[5]	469	1			T264	6		T47	69		T178	18
auto[0]	values[4]	values[6]	252	1			T242	32		T24	21		T283	26
auto[0]	values[4]	values[7]	570	1			T137	19		T211	56		T200	20
auto[0]	values[5]	values[0]	576	1			T253	4		T45	20		T254	6
auto[0]	values[5]	values[1]	376	1			T45	29		T49	20		T172	20
auto[0]	values[5]	values[2]	369	1			T34	20		T46	20		T178	23
auto[0]	values[5]	values[3]	405	1			T35	20		T137	18		T178	22
auto[0]	values[5]	values[4]	517	1			T42	2		T197	20		T284	28
auto[0]	values[5]	values[5]	486	1			T13	26		T34	26		T45	50
auto[0]	values[5]	values[6]	366	1			T41	24		T34	78		T217	20
auto[0]	values[5]	values[7]	536	1			T35	21		T49	19		T261	12
auto[0]	values[6]	values[0]	533	1			T45	71		T49	28		T211	20
auto[0]	values[6]	values[1]	527	1			T34	39		T207	20		T202	109
auto[0]	values[6]	values[2]	870	1			T29	37		T34	20		T227	28
auto[0]	values[6]	values[3]	506	1			T29	29		T34	106		T180	26
auto[0]	values[6]	values[4]	527	1			T2	86		T234	14		T209	8
auto[0]	values[6]	values[5]	508	1			T37	23		T178	20		T226	18
auto[0]	values[6]	values[6]	517	1			T37	34		T45	39		T213	10
auto[0]	values[6]	values[7]	419	1			T217	21		T197	40		T275	12
auto[0]	values[7]	values[0]	473	1			T32	6		T266	4		T47	20
auto[0]	values[7]	values[1]	516	1			T34	20		T35	21		T45	52
auto[0]	values[7]	values[2]	693	1			T178	20		T211	76		T217	20
auto[0]	values[7]	values[3]	645	1			T34	23		T35	21		T178	20
auto[0]	values[7]	values[4]	668	1			T44	20		T49	21		T178	40
auto[0]	values[7]	values[5]	518	1			T35	24		T205	16		T268	28
auto[0]	values[7]	values[6]	270	1			T200	20		T217	19		T207	20
auto[0]	values[7]	values[7]	529	1			T45	19		T47	26		T197	48
auto[1]	values[0]	values[0]	12	1			T194	1		T285	2		T219	3
auto[1]	values[0]	values[1]	10	1			T217	2		T236	2		T82	1
auto[1]	values[0]	values[2]	7	1			T45	2		T207	2		T257	1
auto[1]	values[0]	values[3]	3	1			T44	1		T239	1		T286	1
auto[1]	values[0]	values[4]	9	1			T34	4		T201	2		T287	1
auto[1]	values[0]	values[5]	8	1			T236	1		T288	2		T277	1
auto[1]	values[0]	values[6]	6	1			T260	2		T289	1		T290	3
auto[1]	values[0]	values[7]	2	1			T291	2		-	-		-	-
auto[1]	values[1]	values[0]	9	1			T45	1		T49	1		T232	2
auto[1]	values[1]	values[1]	9	1			T232	2		T274	4		T292	1
auto[1]	values[1]	values[2]	5	1			T286	3		T293	2		-	-
auto[1]	values[1]	values[3]	13	1			T277	6		T294	1		T295	2
auto[1]	values[1]	values[4]	18	1			T49	1		T197	1		T196	1
auto[1]	values[1]	values[5]	5	1			T204	1		T24	1		T296	2
auto[1]	values[1]	values[6]	5	1			T24	2		T297	2		T163	1
auto[1]	values[1]	values[7]	8	1			T44	1		T137	2		T178	1
auto[1]	values[2]	values[0]	12	1			T33	4		T34	3		T45	2
auto[1]	values[2]	values[1]	5	1			T34	1		T45	1		T224	1
auto[1]	values[2]	values[2]	8	1			T34	2		T37	1		T45	1
auto[1]	values[2]	values[3]	12	1			T46	2		T207	1		T232	1
auto[1]	values[2]	values[4]	6	1			T201	1		T221	2		T271	1
auto[1]	values[2]	values[5]	6	1			T207	1		T222	1		T285	1
auto[1]	values[2]	values[6]	4	1			T204	1		T219	1		T296	2
auto[1]	values[2]	values[7]	7	1			T257	1		T89	1		T60	2
auto[1]	values[3]	values[0]	8	1			T35	2		T172	2		T200	1
auto[1]	values[3]	values[1]	10	1			T280	4		T221	1		T277	1
auto[1]	values[3]	values[2]	14	1			T48	6		T200	1		T197	1
auto[1]	values[3]	values[3]	13	1			T248	1		T298	1		T294	1
auto[1]	values[3]	values[4]	11	1			T299	1		T221	5		T285	1
auto[1]	values[3]	values[5]	5	1			T211	2		T200	1		T194	2
auto[1]	values[3]	values[6]	10	1			T273	5		T300	1		T301	2
auto[1]	values[3]	values[7]	3	1			T44	2		T302	1		-	-
auto[1]	values[4]	values[0]	6	1			T297	2		T285	1		T303	1
auto[1]	values[4]	values[1]	1	1			T304	1		-	-		-	-
auto[1]	values[4]	values[2]	6	1			T200	2		T294	2		T305	2
auto[1]	values[4]	values[3]	13	1			T198	1		T236	2		T273	3
auto[1]	values[4]	values[4]	9	1			T46	3		T211	2		T194	2
auto[1]	values[4]	values[5]	7	1			T178	2		T198	1		T236	2
auto[1]	values[4]	values[6]	6	1			T24	3		T82	1		T160	2
auto[1]	values[4]	values[7]	13	1			T137	1		T194	3		T257	2
auto[1]	values[5]	values[0]	6	1			T47	1		T198	2		T287	1
auto[1]	values[5]	values[1]	9	1			T45	3		T49	2		T198	2
auto[1]	values[5]	values[2]	7	1			T46	1		T178	1		T198	1
auto[1]	values[5]	values[3]	25	1			T137	2		T172	1		T260	2
auto[1]	values[5]	values[4]	3	1			T196	1		T277	1		T161	1
auto[1]	values[5]	values[5]	6	1			T137	3		T306	2		T292	1
auto[1]	values[5]	values[6]	2	1			T306	1		T307	1		-	-
auto[1]	values[5]	values[7]	9	1			T49	1		T207	3		T260	1
auto[1]	values[6]	values[0]	6	1			T45	1		T207	1		T287	2
auto[1]	values[6]	values[1]	6	1			T202	3		T294	1		T306	2
auto[1]	values[6]	values[2]	11	1			T194	1		T160	2		T274	3
auto[1]	values[6]	values[3]	5	1			T277	1		T161	1		T306	1
auto[1]	values[6]	values[4]	9	1			T44	2		T308	2		T306	1
auto[1]	values[6]	values[5]	11	1			T201	2		T299	2		T300	2
auto[1]	values[6]	values[6]	8	1			T45	3		T207	1		T161	3
auto[1]	values[6]	values[7]	8	1			T197	1		T271	3		T309	1
auto[1]	values[7]	values[0]	8	1			T211	2		T160	2		T306	1
auto[1]	values[7]	values[1]	14	1			T45	6		T237	1		T221	1
auto[1]	values[7]	values[2]	14	1			T196	1		T300	1		T59	2
auto[1]	values[7]	values[3]	10	1			T34	1		T35	1		T248	3
auto[1]	values[7]	values[4]	10	1			T49	1		T236	2		T302	3
auto[1]	values[7]	values[5]	8	1			T35	1		T248	2		T310	1
auto[1]	values[7]	values[6]	7	1			T217	1		T24	1		T238	2
auto[1]	values[7]	values[7]	7	1			T45	1		T47	1		T302	3