Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2849

1

T1

1

T6

23

T7

1

auto[1]

2760

1

T6

20

T11

10

T14

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3089

1

T7

1

T11

24

T16

5

auto[1]

2520

1

T1

1

T6

43

T14

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4438

1

T1

1

T6

43

T7

1

auto[1]

1171

1

T11

6

T16

3

T17

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1148	1			T6	10		T7	1		T11	5
valid[1]	1124	1			T1	1		T6	5		T11	4
valid[2]	1153	1			T6	12		T11	3		T14	1
valid[3]	1077	1			T6	5		T11	8		T14	1
valid[4]	1107	1			T6	11		T11	4		T15	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	216	1			T7	1		T11	1		T17	4
auto[0]	auto[0]	valid[0]	auto[1]	248	1			T6	6		T15	1		T17	1
auto[0]	auto[0]	valid[1]	auto[0]	191	1			T17	1		T31	2		T51	1
auto[0]	auto[0]	valid[1]	auto[1]	257	1			T1	1		T6	3		T15	1
auto[0]	auto[0]	valid[2]	auto[0]	189	1			T11	3		T16	1		T17	2
auto[0]	auto[0]	valid[2]	auto[1]	274	1			T6	7		T15	2		T17	1
auto[0]	auto[0]	valid[3]	auto[0]	190	1			T11	7		T17	1		T30	3
auto[0]	auto[0]	valid[3]	auto[1]	256	1			T6	1		T15	1		T17	4
auto[0]	auto[0]	valid[4]	auto[0]	181	1			T17	1		T31	3		T51	1
auto[0]	auto[0]	valid[4]	auto[1]	242	1			T6	6		T15	3		T18	2
auto[0]	auto[1]	valid[0]	auto[0]	174	1			T11	1		T17	4		T30	2
auto[0]	auto[1]	valid[0]	auto[1]	284	1			T6	4		T15	2		T16	1
auto[0]	auto[1]	valid[1]	auto[0]	200	1			T11	2		T30	1		T31	3
auto[0]	auto[1]	valid[1]	auto[1]	219	1			T6	2		T15	3		T17	1
auto[0]	auto[1]	valid[2]	auto[0]	197	1			T16	1		T51	1		T55	2
auto[0]	auto[1]	valid[2]	auto[1]	252	1			T6	5		T14	1		T15	4
auto[0]	auto[1]	valid[3]	auto[0]	178	1			T11	1		T17	3		T30	2
auto[0]	auto[1]	valid[3]	auto[1]	239	1			T6	4		T14	1		T15	2
auto[0]	auto[1]	valid[4]	auto[0]	202	1			T11	3		T30	1		T31	1
auto[0]	auto[1]	valid[4]	auto[1]	249	1			T6	5		T15	1		T18	2
auto[1]	auto[0]	valid[0]	auto[0]	106	1			T11	1		T31	1		T51	1
auto[1]	auto[0]	valid[1]	auto[0]	140	1			T11	2		T17	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	127	1			T31	2		T51	1		T55	1
auto[1]	auto[0]	valid[3]	auto[0]	103	1			T30	1		T51	1		T179	1
auto[1]	auto[0]	valid[4]	auto[0]	129	1			T31	2		T51	2		T54	1
auto[1]	auto[1]	valid[0]	auto[0]	120	1			T11	2		T16	1		T30	2
auto[1]	auto[1]	valid[1]	auto[0]	117	1			T31	1		T51	1		T55	2
auto[1]	auto[1]	valid[2]	auto[0]	114	1			T16	1		T17	3		T30	1
auto[1]	auto[1]	valid[3]	auto[0]	111	1			T17	1		T30	1		T31	2
auto[1]	auto[1]	valid[4]	auto[0]	104	1			T11	1		T16	1		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal