Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76136

1

T7

8

T11

420

T16

115

auto[1]

26417

1

T1

1

T6

433

T14

31

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74907

1

T1

1

T6

433

T7

7

auto[1]

27646

1

T7

1

T11

140

T16

58

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	52822	1			T1	1		T6	231		T7	5
others[1]	8600	1			T6	22		T7	2		T11	40
others[2]	8626	1			T6	42		T7	1		T11	37
others[3]	9874	1			T6	38		T11	41		T14	3
interest[1]	5631	1			T6	23		T11	20		T14	1
interest[4]	34509	1			T1	1		T6	153		T7	5
interest[64]	17000	1			T6	77		T11	59		T14	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24875	1			T7	5		T11	146		T16	26
auto[0]	auto[0]	others[1]	4127	1			T7	1		T11	25		T16	6
auto[0]	auto[0]	others[2]	4106	1			T7	1		T11	23		T16	4
auto[0]	auto[0]	others[3]	4672	1			T11	31		T16	7		T17	33
auto[0]	auto[0]	interest[1]	2641	1			T11	15		T16	3		T17	18
auto[0]	auto[0]	interest[4]	16098	1			T7	5		T11	91		T16	13
auto[0]	auto[0]	interest[64]	8069	1			T11	40		T16	11		T17	62
auto[0]	auto[1]	others[0]	13790	1			T1	1		T6	231		T14	14
auto[0]	auto[1]	others[1]	2180	1			T6	22		T14	3		T16	1
auto[0]	auto[1]	others[2]	2146	1			T6	42		T14	1		T16	3
auto[0]	auto[1]	others[3]	2552	1			T6	38		T14	3		T16	3
auto[0]	auto[1]	interest[1]	1465	1			T6	23		T14	1		T16	3
auto[0]	auto[1]	interest[4]	9172	1			T1	1		T6	153		T14	8
auto[0]	auto[1]	interest[64]	4284	1			T6	77		T14	9		T16	7
auto[1]	auto[0]	others[0]	14157	1			T11	77		T16	34		T17	110
auto[1]	auto[0]	others[1]	2293	1			T7	1		T11	15		T16	3
auto[1]	auto[0]	others[2]	2374	1			T11	14		T16	3		T17	26
auto[1]	auto[0]	others[3]	2650	1			T11	10		T16	4		T17	23
auto[1]	auto[0]	interest[1]	1525	1			T11	5		T16	7		T17	8
auto[1]	auto[0]	interest[4]	9239	1			T11	51		T16	20		T17	78
auto[1]	auto[0]	interest[64]	4647	1			T11	19		T16	7		T17	36

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal