Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	749	1			T35	8		T69	11		T46	10
all_values[1]	749	1			T35	8		T69	11		T46	10
all_values[2]	749	1			T35	8		T69	11		T46	10
all_values[3]	749	1			T35	8		T69	11		T46	10
all_values[4]	749	1			T35	8		T69	11		T46	10
all_values[5]	749	1			T35	8		T69	11		T46	10
all_values[6]	749	1			T35	8		T69	11		T46	10
all_values[7]	749	1			T35	8		T69	11		T46	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3202

1

T35

34

T69

49

T46

35

auto[1]

2790

1

T35

30

T69

39

T46

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T35

30

T69

37

T46

34

auto[1]

3519

1

T35

34

T69

51

T46

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3486

1

T35

41

T69

54

T46

48

auto[1]

2506

1

T35

23

T69

34

T46

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T35	6		T69	2		T137	2
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T69	2		T174	1		T175	2
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T35	1		T69	4		T137	7
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T46	4		T138	2		T175	1
all_values[0]	auto[1]	auto[0]	auto[1]	157	1			T69	3		T46	3		T137	1
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T35	1		T46	3		T137	8
all_values[1]	auto[0]	auto[0]	auto[0]	139	1			T35	3		T69	4		T46	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T138	2		T176	1		T177	1
all_values[1]	auto[0]	auto[1]	auto[0]	120	1			T35	3		T69	1		T46	2
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T69	2		T46	2		T137	3
all_values[1]	auto[1]	auto[0]	auto[1]	166	1			T69	1		T46	1		T137	3
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T35	2		T69	3		T46	3
all_values[2]	auto[0]	auto[0]	auto[0]	170	1			T35	1		T69	5		T46	2
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T46	2		T137	4		T138	2
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T35	2		T69	2		T46	2
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T35	2		T46	1		T137	1
all_values[2]	auto[1]	auto[0]	auto[1]	159	1			T35	1		T69	1		T46	2
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T35	2		T69	3		T46	1
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T35	2		T46	2		T137	1
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T35	1		T69	2		T46	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T69	1		T46	4		T137	4
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T35	1		T69	2		T46	1
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T35	2		T69	5		T46	1
all_values[3]	auto[1]	auto[1]	auto[1]	131	1			T35	2		T69	1		T46	1
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T35	2		T69	2		T46	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T35	1		T69	1		T137	1
all_values[4]	auto[0]	auto[1]	auto[0]	126	1			T35	1		T46	2		T137	3
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T69	2		T46	2		T138	2
all_values[4]	auto[1]	auto[0]	auto[1]	189	1			T35	2		T69	3		T46	4
all_values[4]	auto[1]	auto[1]	auto[1]	142	1			T35	2		T69	3		T46	1
all_values[5]	auto[0]	auto[0]	auto[0]	226	1			T35	2		T69	4		T46	2
all_values[5]	auto[0]	auto[1]	auto[0]	202	1			T35	3		T69	3		T46	5
all_values[5]	auto[1]	auto[0]	auto[1]	184	1			T35	2		T69	1		T46	1
all_values[5]	auto[1]	auto[1]	auto[1]	137	1			T35	1		T69	3		T46	2
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T35	4		T69	3		T46	2
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T69	3		T137	2		T176	1
all_values[6]	auto[0]	auto[1]	auto[0]	115	1			T69	1		T46	4		T138	2
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T35	1		T46	1		T137	3
all_values[6]	auto[1]	auto[0]	auto[1]	159	1			T35	2		T69	4		T46	1
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T35	1		T46	2		T137	2
all_values[7]	auto[0]	auto[0]	auto[0]	168	1			T69	2		T46	4		T137	4
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T35	2		T137	1		T175	2
all_values[7]	auto[0]	auto[1]	auto[0]	133	1			T69	3		T137	6		T138	6
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T35	3		T69	3		T137	1
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T35	1		T69	1		T46	4
all_values[7]	auto[1]	auto[1]	auto[1]	131	1			T35	2		T69	2		T46	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal