Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7704779	1			T3	1		T4	1		T5	90492
all_values[1]	7704779	1			T3	1		T4	1		T5	90492
all_values[2]	7704779	1			T3	1		T4	1		T5	90492
all_values[3]	7704779	1			T3	1		T4	1		T5	90492
all_values[4]	7704779	1			T3	1		T4	1		T5	90492
all_values[5]	7704779	1			T3	1		T4	1		T5	90492
all_values[6]	7704779	1			T3	1		T4	1		T5	90492
all_values[7]	7704779	1			T3	1		T4	1		T5	90492

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60051573

1

T3

8

T4

8

T5

723936

auto[1]

1586659

1

T27

34

T61

81

T62

108861

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61559684

1

T3

8

T4

8

T5

722571

auto[1]

78548

1

T5

1365

T8

591

T11

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7402844	1			T3	1		T4	1		T5	89739
all_values[0]	auto[0]	auto[1]	45242	1			T5	753		T8	304		T11	10
all_values[0]	auto[1]	auto[0]	255348	1			T61	5		T62	26933		T44	2
all_values[0]	auto[1]	auto[1]	1345	1			T27	2		T61	5		T62	281
all_values[1]	auto[0]	auto[0]	7438119	1			T3	1		T4	1		T5	89977
all_values[1]	auto[0]	auto[1]	21203	1			T5	515		T8	171		T13	112
all_values[1]	auto[1]	auto[0]	244838	1			T27	7		T61	7		T62	2
all_values[1]	auto[1]	auto[1]	619	1			T44	2		T145	7		T133	75
all_values[2]	auto[0]	auto[0]	7654770	1			T3	1		T4	1		T5	90395
all_values[2]	auto[0]	auto[1]	7829	1			T5	97		T8	116		T13	49
all_values[2]	auto[1]	auto[0]	42003	1			T27	1		T61	2		T44	4
all_values[2]	auto[1]	auto[1]	177	1			T61	6		T62	1		T44	2
all_values[3]	auto[0]	auto[0]	7548960	1			T3	1		T4	1		T5	90492
all_values[3]	auto[0]	auto[1]	223	1			T61	6		T44	2		T45	1
all_values[3]	auto[1]	auto[0]	155415	1			T27	2		T61	3		T62	27213
all_values[3]	auto[1]	auto[1]	181	1			T61	2		T62	2		T44	2
all_values[4]	auto[0]	auto[0]	7521995	1			T3	1		T4	1		T5	90492
all_values[4]	auto[0]	auto[1]	189	1			T124	1		T61	2		T44	2
all_values[4]	auto[1]	auto[0]	182394	1			T27	7		T61	11		T62	1
all_values[4]	auto[1]	auto[1]	201	1			T61	6		T44	1		T145	8
all_values[5]	auto[0]	auto[0]	7501956	1			T3	1		T4	1		T5	90492
all_values[5]	auto[0]	auto[1]	377	1			T20	4		T27	1		T150	2
all_values[5]	auto[1]	auto[0]	202276	1			T27	3		T61	8		T62	27213
all_values[5]	auto[1]	auto[1]	170	1			T27	2		T61	4		T62	1
all_values[6]	auto[0]	auto[0]	7479398	1			T3	1		T4	1		T5	90492
all_values[6]	auto[0]	auto[1]	174	1			T27	1		T61	5		T45	2
all_values[6]	auto[1]	auto[0]	225006	1			T27	2		T61	7		T44	3
all_values[6]	auto[1]	auto[1]	201	1			T27	2		T61	6		T44	3
all_values[7]	auto[0]	auto[0]	7428101	1			T3	1		T4	1		T5	90492
all_values[7]	auto[0]	auto[1]	193	1			T27	2		T61	6		T45	3
all_values[7]	auto[1]	auto[0]	276261	1			T27	6		T61	5		T62	27211
all_values[7]	auto[1]	auto[1]	224	1			T61	4		T62	3		T44	4