Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39779	1			T3	4		T5	331		T6	22
auto[SpiFlashAddrCfg]	9012	1			T3	4		T5	58		T8	72
auto[SpiFlashAddr3b]	10484	1			T3	2		T5	84		T8	88
auto[SpiFlashAddr4b]	8902	1			T3	8		T5	56		T8	62

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38743

1

T5

217

T6

22

T8

317

auto[1]

29434

1

T3

18

T5

312

T8

195

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37963

1

T3

12

T5

214

T6

22

auto[1]

30214

1

T3

6

T5

315

T8

235

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45329	1			T3	6		T5	372		T6	22
values[1]	1235	1			T5	4		T8	7		T11	4
values[2]	1733	1			T5	11		T8	5		T11	6
values[3]	1696	1			T5	14		T8	14		T11	2
values[4]	1730	1			T5	12		T8	10		T12	6
values[5]	1752	1			T5	12		T8	14		T11	3
values[6]	1696	1			T5	13		T8	7		T13	11
values[7]	1576	1			T5	8		T8	21		T11	3
values[8]	11430	1			T3	12		T5	83		T8	89

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36979

1

T3

18

T6

22

T8

512

auto[1]

31198

1

T5

529

T11

157

T15

152

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

65688

1

T3

18

T5

500

T6

22

write

2489

1

T5

29

T8

18

T11

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23119

1

T3

10

T5

147

T6

22

valids[0x1]

45058

1

T3

8

T5

382

T8

342

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1814	1			T5	18		T8	9		T11	9
internal_process_ops[0x5a]	1759	1			T5	22		T8	14		T11	5
internal_process_ops[0x05]	23690	1			T5	183		T8	194		T11	42
internal_process_ops[0x35]	1807	1			T3	4		T5	16		T8	9
internal_process_ops[0x15]	1764	1			T5	14		T8	9		T11	2
internal_process_ops[0x03]	1365	1			T3	4		T5	3		T8	15
internal_process_ops[0x0b]	1263	1			T5	4		T8	11		T13	10
internal_process_ops[0x3b]	1307	1			T5	3		T8	15		T11	2
internal_process_ops[0x6b]	1253	1			T3	4		T5	3		T8	9
internal_process_ops[0xbb]	1327	1			T5	4		T8	11		T11	3
internal_process_ops[0xeb]	1358	1			T5	3		T8	8		T11	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67000

1

T3

18

T5

512

T6

22

auto[1]

1177

1

T5

17

T8

13

T11

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65743

1

T3

18

T5

499

T6

22

auto[1]

2434

1

T5

30

T8

25

T11

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12275

1

T6

22

T8

197

T13

179

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8505

1

T3

4

T8

88

T13

292

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2523

1

T8

38

T13

14

T27

15

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2230

1

T3

4

T8

31

T13

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2923

1

T8

37

T12

2

T13

22

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2549

1

T3

2

T8

43

T13

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2637

1

T8

35

T12

16

T13

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2106

1

T3

8

T8

25

T13

32

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

102

1

T8

3

T27

1

T29

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

55

1

T13

1

T27

1

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T13

3

T33

1

T22

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T8

2

T33

2

T34

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T31

2

T34

2

T22

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T8

1

T13

2

T27

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

78

1

T27

1

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T8

2

T13

6

T27

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T31

2

T30

1

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

58

1

T8

4

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T8

2

T13

1

T33

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T8

2

T13

1

T29

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

104

1

T31

1

T32

4

T34

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

65

1

T8

2

T13

3

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

67

1

T13

1

T34

5

T147

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

70

1

T13

1

T27

2

T31

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10982

1

T5

147

T11

27

T15

56

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7401

1

T5

177

T11

56

T15

30

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1878

1

T5

20

T11

10

T15

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1730

1

T5

33

T11

9

T15

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2328

1

T5

29

T11

14

T15

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2069

1

T5

47

T11

10

T15

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1967

1

T5

15

T11

9

T15

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1585

1

T5

32

T11

10

T15

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T5

1

T11

1

T43

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T5

1

T11

2

T27

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T5

2

T11

1

T43

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T5

3

T11

2

T43

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

79

1

T5

1

T38

2

T148

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T43

1

T148

2

T60

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T5

1

T15

1

T38

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T5

3

T43

5

T38

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

59

1

T5

2

T11

1

T38

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

84

1

T15

2

T43

2

T149

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T15

1

T43

1

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T5

6

T38

1

T60

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

72

1

T5

1

T11

3

T148

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

65

1

T11

1

T15

1

T60

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T5

4

T11

1

T148

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

78

1

T5

4

T43

3

T38

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4929	1			T3	2		T6	22		T8	74
auto[0]	values[0]	valids[0x1]	19183	1			T3	4		T8	271		T13	450
auto[0]	values[1]	valids[0x1]	657	1			T8	7		T13	3		T27	6
auto[0]	values[2]	valids[0x0]	644	1			T8	5		T13	11		T27	2
auto[0]	values[2]	valids[0x1]	340	1			T13	5		T29	1		T31	3
auto[0]	values[3]	valids[0x0]	604	1			T8	10		T13	3		T27	4
auto[0]	values[3]	valids[0x1]	330	1			T8	4		T13	4		T27	3
auto[0]	values[4]	valids[0x0]	564	1			T8	5		T12	2		T13	3
auto[0]	values[4]	valids[0x1]	389	1			T8	5		T12	4		T13	3
auto[0]	values[5]	valids[0x0]	672	1			T8	9		T13	6		T31	12
auto[0]	values[5]	valids[0x1]	348	1			T8	5		T13	6		T27	1
auto[0]	values[6]	valids[0x0]	616	1			T8	5		T13	4		T41	4
auto[0]	values[6]	valids[0x1]	372	1			T8	2		T13	7		T27	5
auto[0]	values[7]	valids[0x0]	553	1			T8	11		T12	8		T13	3
auto[0]	values[7]	valids[0x1]	343	1			T8	10		T13	2		T27	2
auto[0]	values[8]	valids[0x0]	4015	1			T3	8		T8	51		T12	4
auto[0]	values[8]	valids[0x1]	2420	1			T3	4		T8	38		T13	18
auto[1]	values[0]	valids[0x0]	4813	1			T5	74		T11	26		T15	21
auto[1]	values[0]	valids[0x1]	16404	1			T5	298		T11	78		T15	82
auto[1]	values[1]	valids[0x1]	578	1			T5	4		T11	4		T15	3
auto[1]	values[2]	valids[0x0]	492	1			T5	6		T11	4		T43	9
auto[1]	values[2]	valids[0x1]	257	1			T5	5		T11	2		T15	3
auto[1]	values[3]	valids[0x0]	477	1			T5	6		T27	1		T43	14
auto[1]	values[3]	valids[0x1]	285	1			T5	8		T11	2		T15	1
auto[1]	values[4]	valids[0x0]	466	1			T5	8		T15	1		T124	2
auto[1]	values[4]	valids[0x1]	311	1			T5	4		T15	3		T43	4
auto[1]	values[5]	valids[0x0]	423	1			T5	4		T11	3		T15	2
auto[1]	values[5]	valids[0x1]	309	1			T5	8		T15	6		T27	1
auto[1]	values[6]	valids[0x0]	431	1			T5	6		T15	3		T43	16
auto[1]	values[6]	valids[0x1]	277	1			T5	7		T43	2		T38	2
auto[1]	values[7]	valids[0x0]	413	1			T5	5		T11	2		T15	1
auto[1]	values[7]	valids[0x1]	267	1			T5	3		T11	1		T15	2
auto[1]	values[8]	valids[0x0]	3007	1			T5	38		T11	21		T15	15
auto[1]	values[8]	valids[0x1]	1988	1			T5	45		T11	14		T15	9