Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18753

1

T3

1

T4

2

T5

155

auto[1]

24065

1

T5

197

T8

190

T11

41

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15883

1

T3

1

T4

2

T5

139

auto[1]

26935

1

T5

213

T8

212

T11

48

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6904	1			T3	1		T5	32		T6	6
auto[524288:1048575]	5110	1			T5	26		T6	1		T8	32
auto[1048576:1572863]	4852	1			T5	21		T6	1		T8	28
auto[1572864:2097151]	4652	1			T5	85		T6	3		T8	23
auto[2097152:2621439]	5792	1			T4	2		T5	65		T6	1
auto[2621440:3145727]	4757	1			T5	35		T8	34		T11	17
auto[3145728:3670015]	5687	1			T5	43		T8	36		T12	4
auto[3670016:4194303]	5064	1			T5	45		T6	7		T8	54

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41973

1

T3

1

T4

2

T5

344

auto[1]

845

1

T5

8

T8

17

T13

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34108

1

T3

1

T4

2

T5

323

auto[1]

8710

1

T5

29

T6

10

T8

109

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1879	1			T3	1		T5	13		T6	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	758	1			T5	3		T8	2		T11	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1350	1			T5	11		T8	5		T11	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	495	1			T5	3		T8	4		T11	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1381	1			T5	8		T6	1		T8	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	506	1			T5	6		T8	6		T13	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1174	1			T5	22		T8	8		T11	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	510	1			T5	10		T8	4		T11	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1406	1			T4	2		T5	15		T8	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	506	1			T5	11		T8	4		T11	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1203	1			T5	17		T8	8		T11	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	461	1			T5	4		T8	4		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1249	1			T5	9		T8	2		T12	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	447	1			T5	3		T13	8		T15	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1290	1			T5	8		T6	3		T8	17
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	533	1			T5	2		T8	4		T11	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	310	1			T5	1		T6	1		T13	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	138	1			T5	1		T29	1		T43	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	325	1			T5	3		T6	1		T8	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	149	1			T5	2		T8	3		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	264	1			T8	2		T31	1		T194	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	124	1			T11	1		T38	1		T149	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	277	1			T6	3		T8	1		T27	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	107	1			T8	1		T38	2		T149	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	362	1			T6	1		T8	14		T11	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	158	1			T8	6		T11	1		T15	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	332	1			T8	2		T27	6		T31	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	135	1			T8	2		T27	2		T31	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	330	1			T5	1		T8	14		T13	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	132	1			T5	1		T8	7		T13	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	315	1			T5	1		T6	4		T8	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	147	1			T15	4		T31	1		T43	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	294	1			T5	4		T8	1		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2927	1			T5	10		T8	10		T11	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	250	1			T5	3		T8	3		T11	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2023	1			T5	4		T8	14		T11	16
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	228	1			T5	2		T8	1		T13	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1879	1			T5	5		T8	13		T13	79
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	208	1			T5	6		T8	2		T27	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1972	1			T5	47		T8	5		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	281	1			T5	5		T8	2		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2329	1			T5	34		T8	44		T11	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	207	1			T5	5		T8	2		T11	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1695	1			T5	9		T8	8		T11	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	243	1			T5	1		T13	2		T27	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2299	1			T5	28		T13	41		T27	22
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	233	1			T5	3		T8	6		T13	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1892	1			T5	12		T8	26		T13	54
auto[1]	auto[1]	auto[0:524287]	auto[0]	61	1			T38	1		T22	3		T195	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	537	1			T38	1		T22	4		T195	23
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	50	1			T27	1		T31	3		T149	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	468	1			T27	64		T31	18		T149	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	57	1			T38	1		T149	4		T22	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	413	1			T38	10		T149	30		T22	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	47	1			T8	1		T38	4		T34	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	357	1			T8	1		T38	70		T34	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	76	1			T8	3		T15	1		T31	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	674	1			T8	27		T15	4		T31	56
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	59	1			T8	1		T149	1		T61	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	665	1			T8	7		T149	7		T61	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	80	1			T8	3		T27	1		T32	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	907	1			T8	10		T27	3		T32	55
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	62	1			T5	1		T15	1		T27	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	592	1			T5	18		T15	5		T27	20

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14793	1			T3	1		T4	2		T5	141
auto[0]	auto[0]	auto[1]	355	1			T5	4		T8	4		T13	4
auto[0]	auto[1]	auto[0]	3505	1			T5	10		T6	10		T8	54
auto[0]	auto[1]	auto[1]	100	1			T8	2		T31	2		T32	1
auto[1]	auto[0]	auto[0]	18651	1			T5	174		T8	129		T11	41
auto[1]	auto[0]	auto[1]	309	1			T5	4		T8	8		T31	8
auto[1]	auto[1]	auto[0]	5024	1			T5	19		T8	50		T15	11
auto[1]	auto[1]	auto[1]	81	1			T8	3		T27	2		T31	4