Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20999

1

T6

22

T8

317

T12

18

auto[1]

15980

1

T3

18

T8

195

T13

380

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4573	1			T8	27		T12	18		T13	20
values[1]	4796	1			T8	143		T13	230		T27	20
values[2]	4385	1			T8	20		T13	64		T27	78
values[3]	5071	1			T13	66		T29	23		T31	71
values[4]	4615	1			T3	18		T8	98		T13	86
values[5]	3949	1			T8	63		T13	83		T27	29
values[6]	4775	1			T6	22		T8	123		T13	72
values[7]	4815	1			T8	38		T27	40		T31	130

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4628	1			T8	20		T27	124		T41	32
values[1]	4807	1			T8	97		T27	20		T29	42
values[2]	4780	1			T3	18		T6	22		T8	104
values[3]	4433	1			T8	90		T13	262		T31	52
values[4]	4695	1			T8	25		T13	122		T27	20
values[5]	4611	1			T8	82		T13	48		T27	57
values[6]	4980	1			T8	74		T13	20		T31	95
values[7]	4045	1			T8	20		T12	18		T13	66

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	331	1			T27	14		T196	4		T144	12
auto[0]	values[0]	values[1]	369	1			T141	16		T167	17		T173	14
auto[0]	values[0]	values[2]	535	1			T8	22		T147	163		T158	9
auto[0]	values[0]	values[3]	279	1			T197	2		T22	12		T177	17
auto[0]	values[0]	values[4]	291	1			T30	8		T33	11		T34	13
auto[0]	values[0]	values[5]	315	1			T22	18		T198	10		T199	26
auto[0]	values[0]	values[6]	316	1			T13	9		T35	47		T161	11
auto[0]	values[0]	values[7]	286	1			T12	18		T200	20		T34	13
auto[0]	values[1]	values[0]	376	1			T8	13		T41	32		T34	14
auto[0]	values[1]	values[1]	280	1			T174	7		T179	17		T134	9
auto[0]	values[1]	values[2]	386	1			T8	64		T31	13		T22	12
auto[0]	values[1]	values[3]	329	1			T13	8		T44	9		T174	75
auto[0]	values[1]	values[4]	315	1			T163	12		T161	9		T158	12
auto[0]	values[1]	values[5]	565	1			T201	34		T33	11		T35	10
auto[0]	values[1]	values[6]	253	1			T8	12		T31	16		T157	14
auto[0]	values[1]	values[7]	398	1			T8	11		T13	53		T27	12
auto[0]	values[2]	values[0]	129	1			T32	27		T33	3		T158	8
auto[0]	values[2]	values[1]	380	1			T30	10		T34	8		T160	19
auto[0]	values[2]	values[2]	210	1			T34	8		T202	12		T174	15
auto[0]	values[2]	values[3]	516	1			T8	6		T34	13		T44	7
auto[0]	values[2]	values[4]	255	1			T13	29		T157	9		T182	9
auto[0]	values[2]	values[5]	308	1			T13	5		T27	50		T22	11
auto[0]	values[2]	values[6]	226	1			T22	8		T44	13		T174	12
auto[0]	values[2]	values[7]	296	1			T27	15		T203	10		T147	14
auto[0]	values[3]	values[0]	355	1			T31	31		T161	11		T44	27
auto[0]	values[3]	values[1]	341	1			T134	99		T182	15		T204	13
auto[0]	values[3]	values[2]	279	1			T13	10		T31	8		T44	10
auto[0]	values[3]	values[3]	300	1			T13	15		T34	11		T161	11
auto[0]	values[3]	values[4]	323	1			T30	9		T34	12		T22	10
auto[0]	values[3]	values[5]	244	1			T13	7		T29	10		T33	7
auto[0]	values[3]	values[6]	506	1			T22	19		T157	52		T134	11
auto[0]	values[3]	values[7]	180	1			T171	6		T147	11		T156	11
auto[0]	values[4]	values[0]	371	1			T69	24		T37	32		T194	8
auto[0]	values[4]	values[1]	309	1			T31	21		T44	7		T158	11
auto[0]	values[4]	values[2]	458	1			T32	8		T191	12		T158	13
auto[0]	values[4]	values[3]	420	1			T8	11		T31	20		T30	29
auto[0]	values[4]	values[4]	275	1			T13	26		T35	9		T175	8
auto[0]	values[4]	values[5]	290	1			T35	60		T157	47		T44	17
auto[0]	values[4]	values[6]	452	1			T8	31		T34	71		T147	13
auto[0]	values[4]	values[7]	246	1			T31	57		T22	9		T44	15
auto[0]	values[5]	values[0]	423	1			T32	37		T170	26		T134	12
auto[0]	values[5]	values[1]	307	1			T8	32		T29	33		T161	14
auto[0]	values[5]	values[2]	456	1			T13	11		T27	10		T33	10
auto[0]	values[5]	values[3]	187	1			T8	15		T22	12		T205	22
auto[0]	values[5]	values[4]	261	1			T158	9		T134	12		T206	52
auto[0]	values[5]	values[5]	308	1			T157	40		T179	11		T167	8
auto[0]	values[5]	values[6]	176	1			T192	8		T30	10		T178	14
auto[0]	values[5]	values[7]	182	1			T32	37		T50	2		T158	12
auto[0]	values[6]	values[0]	293	1			T27	12		T34	13		T22	9
auto[0]	values[6]	values[1]	362	1			T8	37		T27	5		T32	14
auto[0]	values[6]	values[2]	187	1			T6	22		T22	7		T158	7
auto[0]	values[6]	values[3]	315	1			T13	68		T161	14		T182	18
auto[0]	values[6]	values[4]	556	1			T8	18		T34	12		T207	163
auto[0]	values[6]	values[5]	290	1			T8	34		T34	17		T208	26
auto[0]	values[6]	values[6]	420	1			T30	14		T209	2		T34	11
auto[0]	values[6]	values[7]	204	1			T168	6		T166	14		T172	6
auto[0]	values[7]	values[0]	345	1			T31	10		T210	14		T34	51
auto[0]	values[7]	values[1]	447	1			T22	18		T147	10		T157	78
auto[0]	values[7]	values[2]	253	1			T27	10		T44	18		T121	14
auto[0]	values[7]	values[3]	260	1			T30	11		T33	9		T161	13
auto[0]	values[7]	values[4]	295	1			T27	10		T31	99		T70	6
auto[0]	values[7]	values[5]	354	1			T8	11		T22	11		T157	15
auto[0]	values[7]	values[6]	459	1			T179	10		T170	121		T134	11
auto[0]	values[7]	values[7]	366	1			T35	76		T161	14		T193	18
auto[1]	values[0]	values[0]	146	1			T27	6		T179	9		T170	13
auto[1]	values[0]	values[1]	202	1			T167	8		T173	40		T182	11
auto[1]	values[0]	values[2]	216	1			T8	5		T36	10		T147	10
auto[1]	values[0]	values[3]	130	1			T22	8		T177	7		T186	10
auto[1]	values[0]	values[4]	471	1			T30	12		T33	13		T34	7
auto[1]	values[0]	values[5]	242	1			T22	7		T173	64		T211	28
auto[1]	values[0]	values[6]	272	1			T13	11		T35	3		T161	10
auto[1]	values[0]	values[7]	172	1			T34	14		T157	9		T184	14
auto[1]	values[1]	values[0]	260	1			T8	7		T34	9		T170	11
auto[1]	values[1]	values[1]	153	1			T174	13		T179	8		T134	11
auto[1]	values[1]	values[2]	210	1			T8	13		T31	7		T22	8
auto[1]	values[1]	values[3]	292	1			T13	156		T44	11		T174	6
auto[1]	values[1]	values[4]	303	1			T161	11		T158	12		T212	26
auto[1]	values[1]	values[5]	226	1			T33	17		T35	16		T147	5
auto[1]	values[1]	values[6]	243	1			T8	14		T31	79		T157	6
auto[1]	values[1]	values[7]	207	1			T8	9		T13	13		T27	8
auto[1]	values[2]	values[0]	319	1			T32	15		T33	18		T158	17
auto[1]	values[2]	values[1]	159	1			T30	10		T34	12		T160	10
auto[1]	values[2]	values[2]	240	1			T34	44		T174	6		T165	7
auto[1]	values[2]	values[3]	315	1			T8	14		T34	9		T44	16
auto[1]	values[2]	values[4]	155	1			T13	7		T157	11		T182	12
auto[1]	values[2]	values[5]	307	1			T13	23		T27	7		T22	11
auto[1]	values[2]	values[6]	308	1			T22	12		T44	15		T174	115
auto[1]	values[2]	values[7]	262	1			T27	6		T147	6		T157	11
auto[1]	values[3]	values[0]	251	1			T31	9		T161	9		T44	18
auto[1]	values[3]	values[1]	336	1			T134	75		T182	10		T204	11
auto[1]	values[3]	values[2]	410	1			T13	10		T31	23		T44	12
auto[1]	values[3]	values[3]	360	1			T13	11		T34	9		T143	10
auto[1]	values[3]	values[4]	345	1			T30	11		T34	8		T22	14
auto[1]	values[3]	values[5]	221	1			T13	13		T29	13		T33	13
auto[1]	values[3]	values[6]	360	1			T22	27		T157	32		T134	16
auto[1]	values[3]	values[7]	260	1			T147	57		T156	99		T160	13
auto[1]	values[4]	values[0]	210	1			T32	9		T34	13		T174	8
auto[1]	values[4]	values[1]	286	1			T31	8		T44	13		T158	12
auto[1]	values[4]	values[2]	287	1			T3	18		T32	12		T158	8
auto[1]	values[4]	values[3]	247	1			T8	39		T31	32		T30	22
auto[1]	values[4]	values[4]	178	1			T13	60		T35	33		T173	20
auto[1]	values[4]	values[5]	203	1			T35	11		T157	9		T44	3
auto[1]	values[4]	values[6]	224	1			T8	17		T34	8		T147	7
auto[1]	values[4]	values[7]	159	1			T31	7		T22	17		T44	7
auto[1]	values[5]	values[0]	128	1			T32	4		T48	16		T170	4
auto[1]	values[5]	values[1]	330	1			T8	11		T29	9		T161	7
auto[1]	values[5]	values[2]	300	1			T13	72		T27	19		T33	11
auto[1]	values[5]	values[3]	96	1			T8	5		T22	9		T167	11
auto[1]	values[5]	values[4]	145	1			T158	16		T134	24		T204	10
auto[1]	values[5]	values[5]	161	1			T157	7		T179	9		T167	13
auto[1]	values[5]	values[6]	131	1			T30	10		T44	29		T187	10
auto[1]	values[5]	values[7]	358	1			T32	135		T158	13		T134	14
auto[1]	values[6]	values[0]	383	1			T27	92		T34	8		T22	15
auto[1]	values[6]	values[1]	325	1			T8	17		T27	15		T32	6
auto[1]	values[6]	values[2]	137	1			T22	15		T158	13		T213	26
auto[1]	values[6]	values[3]	222	1			T13	4		T161	23		T182	40
auto[1]	values[6]	values[4]	227	1			T8	7		T34	8		T121	4
auto[1]	values[6]	values[5]	252	1			T8	10		T34	3		T121	12
auto[1]	values[6]	values[6]	302	1			T30	6		T34	9		T157	47
auto[1]	values[6]	values[7]	300	1			T166	6		T172	28		T214	6
auto[1]	values[7]	values[0]	308	1			T31	10		T34	15		T157	38
auto[1]	values[7]	values[1]	221	1			T22	24		T147	10		T157	6
auto[1]	values[7]	values[2]	216	1			T27	10		T44	29		T121	6
auto[1]	values[7]	values[3]	165	1			T30	9		T33	23		T161	7
auto[1]	values[7]	values[4]	300	1			T27	10		T31	11		T147	109
auto[1]	values[7]	values[5]	325	1			T8	27		T22	9		T157	5
auto[1]	values[7]	values[6]	332	1			T215	12		T179	19		T170	12
auto[1]	values[7]	values[7]	169	1			T35	6		T161	6		T44	6