Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	504	1			T8	5		T12	2		T13	2
auto[ReadAddrCrossIntoMailbox]	360	1			T8	7		T12	2		T13	1
auto[ReadAddrCrossOutOfMailbox]	385	1			T8	2		T12	6		T13	1
auto[ReadAddrCrossAllMailbox]	256	1			T8	4		T12	4		T13	1
auto[ReadAddrOutsideMailbox]	4208	1			T3	8		T8	51		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2868

1

T3

4

T8

31

T12

9

auto[1]

2845

1

T3

4

T8

38

T12

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1002	1			T3	4		T8	15		T12	4
read_ops[0x0b]	923	1			T8	11		T13	10		T27	3
read_ops[0x3b]	944	1			T8	15		T12	2		T13	4
read_ops[0x6b]	904	1			T3	4		T8	9		T12	4
read_ops[0xbb]	954	1			T8	11		T13	4		T27	4
read_ops[0xeb]	986	1			T8	8		T12	8		T13	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T13	1		T27	1		T31	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T37	2		T32	1		T34	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T8	1		T41	2		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T27	1		T41	2		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T12	1		T41	3		T147	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T12	1		T41	3		T178	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T8	1		T27	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T13	1		T41	1		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	379	1			T3	2		T8	5		T12	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T3	2		T8	8		T12	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T37	2		T30	1		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T13	1		T37	2		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T8	1		T32	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T8	1		T13	1		T161	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T41	2		T161	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T8	1		T41	2		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T22	1		T158	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T8	1		T32	1		T161	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T8	1		T13	1		T27	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	344	1			T8	6		T13	7		T29	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T33	1		T34	1		T22	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T8	1		T22	1		T157	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T8	1		T12	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T8	2		T12	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T13	1		T32	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T27	1		T30	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T8	1		T34	3		T178	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T8	1		T22	1		T178	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T8	4		T27	2		T41	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	368	1			T8	5		T13	3		T27	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T8	1		T27	1		T208	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T30	1		T208	1		T147	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T32	1		T197	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T30	1		T197	1		T35	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T34	1		T208	1		T178	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T35	1		T208	1		T147	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T12	2		T208	2		T191	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T12	2		T30	1		T208	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	326	1			T3	2		T8	4		T13	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	342	1			T3	2		T8	4		T13	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T37	2		T44	1		T173	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T8	2		T37	2		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T22	1		T216	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T147	1		T216	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T32	1		T22	1		T44	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T8	1		T32	2		T44	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T27	1		T22	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T27	1		T32	1		T216	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	376	1			T8	6		T13	1		T27	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	342	1			T8	2		T13	3		T27	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T12	1		T41	1		T32	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T8	1		T12	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T27	1		T147	1		T161	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T8	1		T33	1		T147	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T12	2		T30	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T12	2		T32	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T33	1		T44	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T31	1		T32	1		T34	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	389	1			T8	5		T12	1		T13	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T8	1		T12	1		T13	4