Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7704779	1			T3	1		T4	1		T5	90492
all_pins[1]	7704779	1			T3	1		T4	1		T5	90492
all_pins[2]	7704779	1			T3	1		T4	1		T5	90492
all_pins[3]	7704779	1			T3	1		T4	1		T5	90492
all_pins[4]	7704779	1			T3	1		T4	1		T5	90492
all_pins[5]	7704779	1			T3	1		T4	1		T5	90492
all_pins[6]	7704779	1			T3	1		T4	1		T5	90492
all_pins[7]	7704779	1			T3	1		T4	1		T5	90492

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	61405968	1			T3	8		T4	8		T5	723936
values[0x1]	232264	1			T27	6		T61	33		T62	1104
transitions[0x0=>0x1]	229966	1			T27	5		T61	26		T62	1101
transitions[0x1=>0x0]	229983	1			T27	5		T61	26		T62	1102

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7703367	1			T3	1		T4	1		T5	90492
all_pins[0]	values[0x1]	1412	1			T27	2		T61	5		T62	292
all_pins[0]	transitions[0x0=>0x1]	1185	1			T27	2		T61	5		T62	292
all_pins[0]	transitions[0x1=>0x0]	418	1			T145	6		T134	2		T146	6
all_pins[1]	values[0x0]	7704134	1			T3	1		T4	1		T5	90492
all_pins[1]	values[0x1]	645	1			T44	2		T145	7		T133	78
all_pins[1]	transitions[0x0=>0x1]	594	1			T145	5		T133	78		T134	2
all_pins[1]	transitions[0x1=>0x0]	127	1			T61	6		T62	1		T45	1
all_pins[2]	values[0x0]	7704601	1			T3	1		T4	1		T5	90492
all_pins[2]	values[0x1]	178	1			T61	6		T62	1		T44	2
all_pins[2]	transitions[0x0=>0x1]	139	1			T61	6		T62	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	142	1			T61	2		T62	2		T45	2
all_pins[3]	values[0x0]	7704598	1			T3	1		T4	1		T5	90492
all_pins[3]	values[0x1]	181	1			T61	2		T62	2		T44	2
all_pins[3]	transitions[0x0=>0x1]	150	1			T61	1		T62	2		T44	2
all_pins[3]	transitions[0x1=>0x0]	170	1			T61	5		T44	1		T145	7
all_pins[4]	values[0x0]	7704578	1			T3	1		T4	1		T5	90492
all_pins[4]	values[0x1]	201	1			T61	6		T44	1		T145	8
all_pins[4]	transitions[0x0=>0x1]	157	1			T61	5		T44	1		T145	7
all_pins[4]	transitions[0x1=>0x0]	4550	1			T27	2		T61	3		T62	806
all_pins[5]	values[0x0]	7700185	1			T3	1		T4	1		T5	90492
all_pins[5]	values[0x1]	4594	1			T27	2		T61	4		T62	806
all_pins[5]	transitions[0x0=>0x1]	2816	1			T27	1		T61	4		T62	806
all_pins[5]	transitions[0x1=>0x0]	223051	1			T27	1		T61	6		T44	3
all_pins[6]	values[0x0]	7479950	1			T3	1		T4	1		T5	90492
all_pins[6]	values[0x1]	224829	1			T27	2		T61	6		T44	3
all_pins[6]	transitions[0x0=>0x1]	224763	1			T27	2		T61	2		T145	2
all_pins[6]	transitions[0x1=>0x0]	158	1			T62	3		T44	1		T145	5
all_pins[7]	values[0x0]	7704555	1			T3	1		T4	1		T5	90492
all_pins[7]	values[0x1]	224	1			T61	4		T62	3		T44	4
all_pins[7]	transitions[0x0=>0x1]	162	1			T61	3		T44	3		T145	8
all_pins[7]	transitions[0x1=>0x0]	1367	1			T27	2		T61	4		T62	290