Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4989	1			T8	38		T13	128		T27	29
values[1]	4711	1			T8	51		T13	83		T31	110
values[2]	4813	1			T6	22		T8	70		T31	52
values[3]	3836	1			T8	55		T13	26		T27	61
values[4]	4695	1			T8	40		T13	20		T41	32
values[5]	4820	1			T12	18		T13	232		T27	20
values[6]	4761	1			T3	18		T8	103		T27	20
values[7]	4354	1			T8	155		T13	132		T27	181

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4357	1			T3	18		T8	28		T13	20
values[1]	4789	1			T8	40		T12	18		T13	20
values[2]	4155	1			T8	83		T13	164		T31	72
values[3]	4832	1			T6	22		T8	40		T13	48
values[4]	4621	1			T13	129		T29	23		T31	110
values[5]	4579	1			T8	146		T13	128		T27	20
values[6]	4391	1			T8	112		T27	86		T31	20
values[7]	5255	1			T8	63		T13	112		T27	104

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36425

1

T3

18

T6

22

T8

499

auto[1]

554

1

T8

13

T13

14

T27

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	819	1			T34	79		T147	117		T170	19
auto[0]	values[0]	values[1]	477	1			T13	19		T194	8		T34	20
auto[0]	values[0]	values[2]	471	1			T31	28		T32	20		T217	6
auto[0]	values[0]	values[3]	471	1			T69	24		T144	12		T121	19
auto[0]	values[0]	values[4]	734	1			T37	32		T30	20		T34	20
auto[0]	values[0]	values[5]	812	1			T13	107		T33	44		T44	27
auto[0]	values[0]	values[6]	480	1			T8	38		T27	27		T80	30
auto[0]	values[0]	values[7]	642	1			T32	99		T33	26		T218	30
auto[0]	values[1]	values[0]	416	1			T30	20		T157	36		T170	59
auto[0]	values[1]	values[1]	549	1			T161	37		T44	25		T174	41
auto[0]	values[1]	values[2]	342	1			T8	25		T34	25		T50	2
auto[0]	values[1]	values[3]	593	1			T22	21		T44	20		T179	22
auto[0]	values[1]	values[4]	771	1			T13	83		T31	107		T32	20
auto[0]	values[1]	values[5]	407	1			T8	22		T157	48		T167	20
auto[0]	values[1]	values[6]	713	1			T22	40		T44	20		T176	36
auto[0]	values[1]	values[7]	857	1			T201	34		T157	57		T44	22
auto[0]	values[2]	values[0]	389	1			T219	40		T186	33		T165	23
auto[0]	values[2]	values[1]	1002	1			T8	18		T34	20		T44	101
auto[0]	values[2]	values[2]	614	1			T31	23		T32	49		T34	37
auto[0]	values[2]	values[3]	515	1			T6	22		T30	20		T32	40
auto[0]	values[2]	values[4]	308	1			T170	22		T167	20		T219	18
auto[0]	values[2]	values[5]	635	1			T8	50		T31	27		T200	20
auto[0]	values[2]	values[6]	531	1			T32	40		T22	19		T35	26
auto[0]	values[2]	values[7]	750	1			T157	56		T44	19		T199	26
auto[0]	values[3]	values[0]	489	1			T8	28		T31	31		T34	52
auto[0]	values[3]	values[1]	489	1			T27	21		T31	40		T216	14
auto[0]	values[3]	values[2]	399	1			T22	26		T174	17		T170	20
auto[0]	values[3]	values[3]	389	1			T27	20		T32	20		T220	2
auto[0]	values[3]	values[4]	428	1			T13	22		T29	23		T33	30
auto[0]	values[3]	values[5]	641	1			T8	26		T27	20		T31	94
auto[0]	values[3]	values[6]	295	1			T34	20		T22	20		T147	20
auto[0]	values[3]	values[7]	640	1			T192	8		T33	18		T147	20
auto[0]	values[4]	values[0]	411	1			T41	32		T158	22		T121	20
auto[0]	values[4]	values[1]	633	1			T31	84		T171	6		T173	20
auto[0]	values[4]	values[2]	621	1			T31	20		T141	16		T22	22
auto[0]	values[4]	values[3]	690	1			T158	25		T134	80		T221	80
auto[0]	values[4]	values[4]	502	1			T13	20		T32	84		T167	20
auto[0]	values[4]	values[5]	544	1			T209	2		T34	20		T161	23
auto[0]	values[4]	values[6]	711	1			T8	19		T157	83		T44	20
auto[0]	values[4]	values[7]	527	1			T8	20		T22	25		T147	68
auto[0]	values[5]	values[0]	1040	1			T13	16		T30	20		T22	20
auto[0]	values[5]	values[1]	520	1			T12	18		T27	20		T157	51
auto[0]	values[5]	values[2]	561	1			T13	162		T30	20		T35	45
auto[0]	values[5]	values[3]	605	1			T13	48		T203	10		T147	19
auto[0]	values[5]	values[4]	443	1			T30	23		T48	12		T134	22
auto[0]	values[5]	values[5]	506	1			T179	20		T222	57		T165	26
auto[0]	values[5]	values[6]	605	1			T34	26		T22	21		T147	20
auto[0]	values[5]	values[7]	473	1			T22	24		T44	20		T158	38
auto[0]	values[6]	values[0]	547	1			T3	18		T163	12		T174	20
auto[0]	values[6]	values[1]	372	1			T27	18		T196	4		T34	21
auto[0]	values[6]	values[2]	712	1			T30	27		T34	63		T22	20
auto[0]	values[6]	values[3]	925	1			T8	40		T197	2		T161	20
auto[0]	values[6]	values[4]	353	1			T34	20		T44	20		T158	20
auto[0]	values[6]	values[5]	402	1			T223	16		T179	29		T156	24
auto[0]	values[6]	values[6]	693	1			T8	20		T31	20		T70	6
auto[0]	values[6]	values[7]	690	1			T8	43		T224	2		T191	12
auto[0]	values[7]	values[0]	194	1			T34	24		T44	50		T167	21
auto[0]	values[7]	values[1]	690	1			T8	19		T27	18		T22	20
auto[0]	values[7]	values[2]	347	1			T8	57		T33	18		T22	42
auto[0]	values[7]	values[3]	575	1			T30	19		T143	10		T22	24
auto[0]	values[7]	values[4]	1013	1			T35	81		T157	20		T44	20
auto[0]	values[7]	values[5]	563	1			T8	42		T13	20		T29	39
auto[0]	values[7]	values[6]	297	1			T8	32		T27	55		T33	20
auto[0]	values[7]	values[7]	592	1			T13	110		T27	103		T34	20
auto[1]	values[0]	values[0]	11	1			T147	2		T170	1		T134	2
auto[1]	values[0]	values[1]	6	1			T13	1		T173	2		T187	1
auto[1]	values[0]	values[2]	12	1			T31	1		T225	1		T226	1
auto[1]	values[0]	values[3]	4	1			T121	1		T77	1		T227	1
auto[1]	values[0]	values[4]	9	1			T34	1		T161	3		T228	1
auto[1]	values[0]	values[5]	20	1			T13	1		T33	3		T121	3
auto[1]	values[0]	values[6]	10	1			T27	2		T134	4		T229	3
auto[1]	values[0]	values[7]	11	1			T32	4		T33	2		T204	1
auto[1]	values[1]	values[0]	10	1			T170	1		T167	1		T139	2
auto[1]	values[1]	values[1]	4	1			T230	2		T231	1		T232	1
auto[1]	values[1]	values[2]	3	1			T8	1		T165	1		T233	1
auto[1]	values[1]	values[3]	8	1			T22	1		T179	2		T184	1
auto[1]	values[1]	values[4]	9	1			T31	3		T44	1		T234	1
auto[1]	values[1]	values[5]	5	1			T8	3		T235	2		-	-
auto[1]	values[1]	values[6]	8	1			T156	2		T186	1		T187	1
auto[1]	values[1]	values[7]	16	1			T44	1		T134	2		T156	2
auto[1]	values[2]	values[0]	4	1			T165	1		T236	1		T237	2
auto[1]	values[2]	values[1]	12	1			T8	2		T44	2		T227	6
auto[1]	values[2]	values[2]	14	1			T34	6		T222	1		T238	1
auto[1]	values[2]	values[3]	7	1			T32	2		T44	1		T121	1
auto[1]	values[2]	values[4]	4	1			T219	2		T172	2		-	-
auto[1]	values[2]	values[5]	7	1			T31	2		T35	2		T170	1
auto[1]	values[2]	values[6]	9	1			T32	1		T22	1		T239	1
auto[1]	values[2]	values[7]	12	1			T44	1		T182	3		T77	2
auto[1]	values[3]	values[0]	2	1			T240	2		-	-		-	-
auto[1]	values[3]	values[1]	7	1			T241	2		T242	4		T243	1
auto[1]	values[3]	values[2]	12	1			T174	4		T166	1		T225	2
auto[1]	values[3]	values[3]	2	1			T186	1		T244	1		-	-
auto[1]	values[3]	values[4]	17	1			T13	4		T33	2		T186	1
auto[1]	values[3]	values[5]	11	1			T8	1		T31	1		T156	1
auto[1]	values[3]	values[6]	2	1			T244	1		T245	1		-	-
auto[1]	values[3]	values[7]	13	1			T33	3		T44	1		T167	2
auto[1]	values[4]	values[0]	5	1			T158	3		T170	1		T219	1
auto[1]	values[4]	values[1]	12	1			T156	2		T177	1		T246	1
auto[1]	values[4]	values[2]	9	1			T187	1		T231	2		T247	2
auto[1]	values[4]	values[3]	12	1			T134	2		T221	2		T248	1
auto[1]	values[4]	values[4]	4	1			T182	2		T184	1		T238	1
auto[1]	values[4]	values[5]	5	1			T172	2		T249	2		T47	1
auto[1]	values[4]	values[6]	5	1			T8	1		T157	1		T250	1
auto[1]	values[4]	values[7]	4	1			T182	1		T139	2		T243	1
auto[1]	values[5]	values[0]	16	1			T13	4		T44	1		T167	3
auto[1]	values[5]	values[1]	5	1			T251	2		T77	2		T249	1
auto[1]	values[5]	values[2]	11	1			T13	2		T35	5		T161	1
auto[1]	values[5]	values[3]	5	1			T147	1		T233	1		T252	2
auto[1]	values[5]	values[4]	10	1			T30	1		T48	4		T134	2
auto[1]	values[5]	values[5]	3	1			T172	2		T235	1		-	-
auto[1]	values[5]	values[6]	12	1			T34	1		T167	3		T219	2
auto[1]	values[5]	values[7]	5	1			T158	2		T140	1		T253	2
auto[1]	values[6]	values[0]	3	1			T165	1		T214	1		T254	1
auto[1]	values[6]	values[1]	4	1			T27	2		T34	1		T47	1
auto[1]	values[6]	values[2]	15	1			T34	3		T22	2		T44	2
auto[1]	values[6]	values[3]	15	1			T170	2		T239	1		T169	1
auto[1]	values[6]	values[4]	4	1			T47	2		T255	1		T256	1
auto[1]	values[6]	values[5]	3	1			T225	2		T240	1		-	-
auto[1]	values[6]	values[6]	12	1			T36	2		T44	2		T249	2
auto[1]	values[6]	values[7]	11	1			T166	2		T169	2		T227	1
auto[1]	values[7]	values[0]	1	1			T34	1		-	-		-	-
auto[1]	values[7]	values[1]	7	1			T8	1		T27	2		T184	1
auto[1]	values[7]	values[2]	12	1			T33	3		T173	1		T182	2
auto[1]	values[7]	values[3]	16	1			T30	1		T22	2		T158	1
auto[1]	values[7]	values[4]	12	1			T35	1		T158	3		T174	2
auto[1]	values[7]	values[5]	15	1			T8	2		T29	3		T44	3
auto[1]	values[7]	values[6]	8	1			T8	2		T27	2		T172	2
auto[1]	values[7]	values[7]	12	1			T13	2		T27	1		T121	1