Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2583

1

T5

10

T9

5

T10

12

auto[1]

2586

1

T5

6

T10

7

T16

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T5

16

T9

5

T18

18

auto[1]

2389

1

T10

19

T16

10

T18

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4108

1

T5

12

T9

3

T10

19

auto[1]

1061

1

T5

4

T9

2

T18

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1061	1			T5	5		T10	6		T16	2
valid[1]	1003	1			T5	7		T10	3		T16	2
valid[2]	995	1			T5	3		T9	2		T10	6
valid[3]	1080	1			T9	2		T10	1		T16	1
valid[4]	1030	1			T5	1		T9	1		T10	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	175	1			T5	2		T18	3		T27	1
auto[0]	auto[0]	valid[0]	auto[1]	261	1			T10	4		T16	1		T18	2
auto[0]	auto[0]	valid[1]	auto[0]	154	1			T5	5		T18	1		T28	2
auto[0]	auto[0]	valid[1]	auto[1]	227	1			T10	1		T16	1		T15	1
auto[0]	auto[0]	valid[2]	auto[0]	178	1			T5	1		T27	2		T30	1
auto[0]	auto[0]	valid[2]	auto[1]	220	1			T10	4		T16	1		T18	2
auto[0]	auto[0]	valid[3]	auto[0]	186	1			T9	2		T18	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	246	1			T42	1		T71	2		T43	1
auto[0]	auto[0]	valid[4]	auto[0]	158	1			T9	1		T15	1		T43	2
auto[0]	auto[0]	valid[4]	auto[1]	258	1			T10	3		T16	1		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	162	1			T5	1		T28	1		T29	2
auto[0]	auto[1]	valid[0]	auto[1]	244	1			T10	2		T16	1		T19	3
auto[0]	auto[1]	valid[1]	auto[0]	175	1			T5	2		T18	2		T15	1
auto[0]	auto[1]	valid[1]	auto[1]	235	1			T10	2		T16	1		T19	2
auto[0]	auto[1]	valid[2]	auto[0]	170	1			T18	1		T27	3		T28	1
auto[0]	auto[1]	valid[2]	auto[1]	226	1			T10	2		T16	1		T42	1
auto[0]	auto[1]	valid[3]	auto[0]	187	1			T18	1		T15	1		T27	2
auto[0]	auto[1]	valid[3]	auto[1]	239	1			T10	1		T16	1		T18	1
auto[0]	auto[1]	valid[4]	auto[0]	174	1			T5	1		T18	2		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	233	1			T16	2		T19	3		T42	4
auto[1]	auto[0]	valid[0]	auto[0]	111	1			T5	1		T18	1		T15	2
auto[1]	auto[0]	valid[1]	auto[0]	95	1			T27	1		T29	1		T260	1
auto[1]	auto[0]	valid[2]	auto[0]	107	1			T5	1		T9	2		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	104	1			T18	1		T27	1		T28	2
auto[1]	auto[0]	valid[4]	auto[0]	103	1			T15	1		T29	1		T43	3
auto[1]	auto[1]	valid[0]	auto[0]	108	1			T5	1		T18	1		T43	1
auto[1]	auto[1]	valid[1]	auto[0]	117	1			T18	2		T15	1		T43	1
auto[1]	auto[1]	valid[2]	auto[0]	94	1			T5	1		T75	1		T44	6
auto[1]	auto[1]	valid[3]	auto[0]	118	1			T15	1		T27	1		T28	1
auto[1]	auto[1]	valid[4]	auto[0]	104	1			T18	1		T15	1		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal