Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71922

1

T5

354

T8

30

T9

74

auto[1]

25948

1

T9

6

T10

19

T16

101

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71476

1

T5

225

T8

16

T9

56

auto[1]

26394

1

T5

129

T8

14

T9

24

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	50412	1			T5	175		T8	19		T9	42
others[1]	8165	1			T5	35		T8	2		T9	9
others[2]	8344	1			T5	30		T9	11		T16	10
others[3]	9308	1			T5	21		T8	3		T9	2
interest[1]	5475	1			T5	27		T8	2		T9	3
interest[4]	32964	1			T5	123		T8	12		T9	28
interest[64]	16166	1			T5	66		T8	4		T9	13

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23485	1			T5	118		T8	10		T9	29
auto[0]	auto[0]	others[1]	3746	1			T5	20		T9	4		T18	29
auto[0]	auto[0]	others[2]	3900	1			T5	14		T9	6		T18	22
auto[0]	auto[0]	others[3]	4347	1			T5	13		T8	3		T9	2
auto[0]	auto[0]	interest[1]	2567	1			T5	17		T8	2		T9	1
auto[0]	auto[0]	interest[4]	15299	1			T5	79		T8	4		T9	18
auto[0]	auto[0]	interest[64]	7483	1			T5	43		T8	1		T9	8
auto[0]	auto[1]	others[0]	13642	1			T9	3		T10	19		T16	51
auto[0]	auto[1]	others[1]	2119	1			T9	1		T16	9		T18	7
auto[0]	auto[1]	others[2]	2109	1			T16	10		T18	13		T15	12
auto[0]	auto[1]	others[3]	2483	1			T16	9		T18	12		T15	9
auto[0]	auto[1]	interest[1]	1421	1			T16	6		T18	4		T15	6
auto[0]	auto[1]	interest[4]	9107	1			T9	3		T10	19		T16	32
auto[0]	auto[1]	interest[64]	4174	1			T9	2		T16	16		T18	14
auto[1]	auto[0]	others[0]	13285	1			T5	57		T8	9		T9	10
auto[1]	auto[0]	others[1]	2300	1			T5	15		T8	2		T9	4
auto[1]	auto[0]	others[2]	2335	1			T5	16		T9	5		T18	24
auto[1]	auto[0]	others[3]	2478	1			T5	8		T18	19		T15	15
auto[1]	auto[0]	interest[1]	1487	1			T5	10		T9	2		T18	9
auto[1]	auto[0]	interest[4]	8558	1			T5	44		T8	8		T9	7
auto[1]	auto[0]	interest[64]	4509	1			T5	23		T8	3		T9	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal