Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	811	1			T27	7		T61	17		T62	4
all_values[1]	811	1			T27	7		T61	17		T62	4
all_values[2]	811	1			T27	7		T61	17		T62	4
all_values[3]	811	1			T27	7		T61	17		T62	4
all_values[4]	811	1			T27	7		T61	17		T62	4
all_values[5]	811	1			T27	7		T61	17		T62	4
all_values[6]	811	1			T27	7		T61	17		T62	4
all_values[7]	811	1			T27	7		T61	17		T62	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3437

1

T27

36

T61

80

T62

15

auto[1]

3051

1

T27

20

T61

56

T62

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2670

1

T27

29

T61

44

T62

15

auto[1]

3818

1

T27

27

T61

92

T62

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3758

1

T27

37

T61

66

T62

23

auto[1]

2730

1

T27

19

T61

70

T62

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T61	2		T44	1		T145	4
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T27	3		T61	3		T45	1
all_values[0]	auto[0]	auto[1]	auto[0]	173	1			T61	3		T45	1		T145	3
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T61	2		T62	3		T44	1
all_values[0]	auto[1]	auto[0]	auto[1]	176	1			T27	3		T61	4		T62	1
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T27	1		T61	3		T44	1
all_values[1]	auto[0]	auto[0]	auto[0]	166	1			T27	1		T61	3		T62	1
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T27	2		T61	2		T145	5
all_values[1]	auto[0]	auto[1]	auto[0]	154	1			T27	2		T61	5		T62	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T44	1		T145	2		T146	2
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T27	2		T61	6		T62	1
all_values[1]	auto[1]	auto[1]	auto[1]	141	1			T61	1		T44	2		T145	7
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T27	5		T61	3		T145	6
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T61	1		T62	2		T145	4
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T61	1		T44	1		T45	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T61	3		T44	1		T45	1
all_values[2]	auto[1]	auto[0]	auto[1]	203	1			T27	2		T61	7		T62	1
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T61	2		T62	1		T44	2
all_values[3]	auto[0]	auto[0]	auto[0]	171	1			T27	3		T61	5		T145	4
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T61	2		T145	2		T133	5
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T27	3		T61	2		T62	2
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T62	1		T44	2		T45	1
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T27	1		T61	6		T44	2
all_values[3]	auto[1]	auto[1]	auto[1]	156	1			T61	2		T62	1		T45	1
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T27	3		T61	1		T62	3
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T61	1		T44	2		T145	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T27	2		T61	4		T62	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T61	2		T145	4		T133	2
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T61	4		T145	3		T133	4
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T27	2		T61	5		T44	1
all_values[5]	auto[0]	auto[0]	auto[0]	263	1			T27	1		T61	5		T62	1
all_values[5]	auto[0]	auto[1]	auto[0]	216	1			T27	3		T61	4		T62	2
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T27	1		T61	5		T44	1
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T27	2		T61	3		T62	1
all_values[6]	auto[0]	auto[0]	auto[0]	179	1			T27	1		T61	2		T62	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T61	1		T45	1		T145	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T27	2		T44	1		T45	1
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T27	1		T61	1		T44	1
all_values[6]	auto[1]	auto[0]	auto[1]	161	1			T27	2		T61	5		T62	1
all_values[6]	auto[1]	auto[1]	auto[1]	168	1			T27	1		T61	8		T44	2
all_values[7]	auto[0]	auto[0]	auto[0]	150	1			T27	2		T61	3		T45	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T27	2		T61	3		T62	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T27	1		T61	1		T145	5
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T61	1		T62	1		T44	2
all_values[7]	auto[1]	auto[0]	auto[1]	193	1			T27	2		T61	6		T45	2
all_values[7]	auto[1]	auto[1]	auto[1]	179	1			T61	3		T62	2		T44	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal