Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	324877	1			T1	3779		T2	232		T12	7128
all_values[1]	324877	1			T1	3779		T2	232		T12	7128
all_values[2]	324877	1			T1	3779		T2	232		T12	7128
all_values[3]	324877	1			T1	3779		T2	232		T12	7128
all_values[4]	324877	1			T1	3779		T2	232		T12	7128
all_values[5]	324877	1			T1	3779		T2	232		T12	7128
all_values[6]	324877	1			T1	3779		T2	232		T12	7128
all_values[7]	324877	1			T1	3779		T2	232		T12	7128

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2596414

1

T1

30232

T2

1856

T12

57024

auto[1]

2602

1

T18

23

T31

84

T32

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2596605

1

T1

30232

T2

1856

T12

57014

auto[1]

2411

1

T12

10

T18

18

T100

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	324417	1			T1	3779		T2	232		T12	7128
all_values[0]	auto[0]	auto[1]	132	1			T31	1		T32	2		T38	8
all_values[0]	auto[1]	auto[0]	201	1			T18	2		T31	10		T32	6
all_values[0]	auto[1]	auto[1]	127	1			T18	3		T31	8		T32	2
all_values[1]	auto[0]	auto[0]	324428	1			T1	3779		T2	232		T12	7128
all_values[1]	auto[0]	auto[1]	132	1			T18	1		T31	5		T32	1
all_values[1]	auto[1]	auto[0]	180	1			T31	6		T32	4		T38	14
all_values[1]	auto[1]	auto[1]	137	1			T18	1		T31	3		T38	5
all_values[2]	auto[0]	auto[0]	324397	1			T1	3779		T2	232		T12	7128
all_values[2]	auto[0]	auto[1]	140	1			T18	1		T31	4		T32	5
all_values[2]	auto[1]	auto[0]	212	1			T18	1		T31	6		T32	8
all_values[2]	auto[1]	auto[1]	128	1			T18	3		T31	3		T32	5
all_values[3]	auto[0]	auto[0]	324420	1			T1	3779		T2	232		T12	7128
all_values[3]	auto[0]	auto[1]	119	1			T100	3		T169	4		T31	4
all_values[3]	auto[1]	auto[0]	231	1			T18	3		T31	6		T32	8
all_values[3]	auto[1]	auto[1]	107	1			T31	5		T32	3		T38	7
all_values[4]	auto[0]	auto[0]	324369	1			T1	3779		T2	232		T12	7128
all_values[4]	auto[0]	auto[1]	175	1			T18	2		T31	5		T325	5
all_values[4]	auto[1]	auto[0]	188	1			T18	1		T31	8		T32	8
all_values[4]	auto[1]	auto[1]	145	1			T18	2		T31	2		T32	2
all_values[5]	auto[0]	auto[0]	324186	1			T1	3779		T2	232		T12	7118
all_values[5]	auto[0]	auto[1]	378	1			T12	10		T18	1		T65	1
all_values[5]	auto[1]	auto[0]	196	1			T31	5		T32	6		T38	13
all_values[5]	auto[1]	auto[1]	117	1			T31	4		T32	2		T38	5
all_values[6]	auto[0]	auto[0]	324416	1			T1	3779		T2	232		T12	7128
all_values[6]	auto[0]	auto[1]	152	1			T31	5		T32	4		T38	7
all_values[6]	auto[1]	auto[0]	175	1			T18	4		T31	5		T32	6
all_values[6]	auto[1]	auto[1]	134	1			T31	5		T32	7		T38	7
all_values[7]	auto[0]	auto[0]	324411	1			T1	3779		T2	232		T12	7128
all_values[7]	auto[0]	auto[1]	142	1			T18	2		T32	2		T38	8
all_values[7]	auto[1]	auto[0]	178	1			T18	1		T31	4		T32	3
all_values[7]	auto[1]	auto[1]	146	1			T18	2		T31	4		T32	6